Semiconductor Package Wire Layout for EMI-Resistant Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving compactness and excellent electrical characteristics, particularly in high-frequency applications, due to limitations in integrating multiple devices into a single package and reducing the size and weight of mounting parts, which leads to interference from electromagnetic waves generated by signal wires.
Innovation Solution
A semiconductor package design featuring a substrate with alternately arranged first and second wire groups, where the first wire group includes a signal wire positioned in the second direction of a power/ground wire, and the second wire group has a signal wire positioned opposite to the power/ground wire, with top ends of the wires strategically shifted to minimize interference, along with a molding layer to cover the chips and substrate, optimizing the arrangement of bonding wires to reduce electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple devices are integrated into a single package to reduce size and weight, then compactness is improved, but electromagnetic interference between signal wires increases
Solution Approach 1:
The wire groups are segmented into first wire groups and second wire groups that are alternately arranged. Each wire group contains signal wires and power/ground wires in a specific alternating pattern, which divides the electromagnetic fields and reduces mutual interference between adjacent signal wires.
Solution Approach 2:
The patent applies different arrangement patterns to different regions: first wire groups have signal wires in one direction relative to power/ground wires, while second wire groups have signal wires in the opposite direction. This local variation in arrangement quality optimizes electromagnetic field distribution and minimizes interference in high-frequency applications.
2Object-generated harmful factors
If wire groups are alternately arranged with signal wires and power/ground wires in orthogonal directions, then electromagnetic interference is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric arrangement where first wire groups and second wire groups have mirror-image configurations. The signal wires in first wire groups are positioned in the second direction of power/ground wires, while in second wire groups they are positioned in the opposite direction, creating a balanced asymmetric pattern that simplifies manufacturing while maintaining EMI reduction.
Solution Approach 2:
The patent transitions from planar wire arrangement to three-dimensional alternating layers. Wire groups are arranged in alternating directions with top ends shifted in the first direction, utilizing vertical and horizontal dimensions to achieve EMI reduction without excessive planar complexity.
3Object-generated harmful factors
If bonding apparatus uses different vertical departing distances for different pads, then wire length and interference are optimized, but bonding process time increases
Solution Approach 1:
The bonding apparatus is pre-programmed with different vertical departing distances for different pad types (first power/ground pad, first input/output pad, second input/output pad, second power/ground pad). This preliminary configuration allows the bonding process to automatically optimize wire lengths and spacing without real-time adjustments, reducing overall process time while maintaining interference optimization.
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate including substrate pads, a first semiconductor chip mounted on the substrate and including first chip pads arranged in a first direction of the first semiconductor chip, and a first wire group that connects the substrate pads to the first chip pads and includes a first power/ground wire, a first signal wire, a second signal wire, and a second power/ground wire that are arranged in a second direction that is orthogonal to the first direction. A first top end of the first signal wire is closer horizontally to the first chip pads than is a second top end of the second signal wire.