Power Semiconductor Package Wire Length Reduction

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Solution Overview

Problem

Power semiconductor modules used in motor inverter circuits face reliability issues due to high wiring resistance and parasitic inductance, leading to potential breakdown from reverse induction voltage, and the interface between the resin and die pad peels off due to temperature cycles, causing device failure.

Innovation Solution

The semiconductor device features a sealing body with metal base plates and conductive adhesives that shorten the length of wires coupling semiconductor chips to leads, reducing wiring resistance and parasitic inductance, and incorporates grooves in die pads to anchor the resin and prevent peeling, ensuring reliable operation under high voltage and temperature conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the wiring length between semiconductor chips and leads is reduced, then wiring resistance and parasitic inductance decrease, but the device complexity increases due to the need for precise lead positioning

Engineering Contradiction:
Improvebreakdown resistanceVSAvoidlead positioning precision
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The lead ends are positioned in advance at heights above the metal base plate surfaces before the semiconductor chips are mounted. This preliminary positioning ensures that when the chips are connected via wires, the wiring length is minimized, reducing both wiring resistance and parasitic inductance while maintaining manufacturing feasibility

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The solution moves from a two-dimensional planar arrangement to a three-dimensional configuration by positioning lead ends at different heights above the metal base plate. This vertical dimension allows for shorter wire lengths without increasing horizontal complexity, effectively reducing electrical parameters while maintaining manufacturing simplicity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If the resin sealing body is applied to cover metal base plates, then insulation and protection are improved, but the interface between resin and die pad peels off due to temperature cycles

Engineering Contradiction:
Improveinsulation performanceVSAvoidinterface adhesion
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The metal base plates are selectively positioned to extend above the resin sealing body at specific locations, creating a local quality difference. This allows the resin to provide insulation and protection where needed while the exposed metal base plate areas maintain strong mechanical and thermal bonds with the die pads, preventing peeling at the resin-die pad interface during temperature cycles

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration decreases the likelihood of semiconductor chip breakdown from reverse induction voltage and enhances the reliability of power semiconductor modules by reducing wiring resistance and parasitic inductance, while preventing resin peeling and ensuring effective heat dissipation.

Implementation Method 1

a first semiconductor chip having a first electrode on its lower surface and a second electrode pad and a control electrode pad on its upper surface with the lower surface fixed on an upper surface of the first metal base plate through a conductive adhesive

Methodology Applied
Scientific EffectConduction (electrical): Conduction (electrical)

Implementation Method 2

a metal base plate for diffusing heat generated by semiconductor elements

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 3

a first conductive material electrically coupling the second electrode pad of the first semiconductor chip and the one end of the first lead

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 4

incorporates grooves in die pads to anchor the resin and prevent peeling

Methodology Applied
Scientific EffectMechanical interlocking: Mechanical Fastener

Data Source

PatentUS8629467B2Semiconductor device
Publication Date: 2014.01.14 RENESAS ELECTRONICS CORP
  • US8629467B2 patent drawing
  • US8629467B2 patent drawing
  • US8629467B2 patent drawing

AI summary

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.