Semiconductor Package Wire Reinforcement for POP Reliability

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Solution Overview

Problem

Current semiconductor packages face challenges in reliability and durability due to limitations in connecting substrates and maintaining wire integrity, which affects electrical connections and thermal radiation properties.

Innovation Solution

A semiconductor package design featuring a first substrate with a semiconductor chip, a second substrate spaced apart, bonding wires connecting them, and an under-fill pattern and mold structure to reinforce the connection and improve stiffness, allowing for a package-on-package structure with enhanced reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding wires are used to connect substrates, then electrical connection is achieved, but wire integrity and structural stability deteriorate

Engineering Contradiction:
Improvewire connection reliabilityVSAvoidwire structural strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies composite materials by combining bonding wires with under-fill patterns and mold structures. The under-fill pattern (400) is formed around the bonding wires (300), and the mold structure (950) encapsulates both, creating a composite system where the wire provides electrical connection while the under-fill and mold provide structural support and stability, resolving the contradiction between electrical functionality and structural strength.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent implements beforehand cushioning by forming the under-fill pattern (400) around the bonding wires (300) before final packaging. This under-fill layer acts as a protective cushion that reinforces the wires against mechanical stress and environmental factors, preventing wire damage and maintaining integrity throughout the package lifecycle.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If substrates are spaced apart for package-on-package structure, then integration density is improved, but alignment precision and connection reliability worsen

Engineering Contradiction:
Improveintegration densityVSAvoidsubstrate alignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent uses the mold structure (950) as an intermediary element that connects and aligns the first substrate (1000) and second substrate (2000). The mold structure encapsulates the spaced substrates and provides a rigid framework that maintains precise relative positioning, enabling package-on-package integration while ensuring manufacturing precision through its structural support and alignment features.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If wire connections are reinforced with under-fill patterns, then structural integrity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvewire connection stabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the under-fill pattern (400) formation process. The same under-fill material that reinforces wire connections also serves as part of the encapsulation system and provides structural support for the mold structure (950). This consolidation of functions reduces the need for separate reinforcement components and simplifies the overall manufacturing process while maintaining wire connection stability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4318579A1Semiconductor package
Publication Date: 2024.02.07 SAMSUNG ELECTRONICS CO LTD
  • EP4318579A1 patent drawingFigure 1
  • EP4318579A1 patent drawingFigure 2
  • EP4318579A1 patent drawingFigure 3

AI summary

A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate , a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.