Semiconductor Package Wire Routing for Miniaturization
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Solution Overview
Problem
The challenge is to miniaturize semiconductor packages while maintaining reliability and increasing integration density, as existing technologies struggle to reduce package size without compromising performance and reliability due to the need for high-performance and multi-functional semiconductor chips.
Innovation Solution
The solution involves a semiconductor package design that includes a mounting substrate with bonding pads, semiconductor chips with protrusions, spacer balls, bump balls, and wires that connect the chips to the bonding pads without contacting the protrusions, with the wires formed as folded loops to reduce height and prevent short-circuits, allowing for vertical stacking and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor packages is reduced to satisfy downsizing trends, then the package size decreases, but the reliability and electrical connectivity may be compromised due to proximity of components
Solution Approach 1:
The wire is configured in a folded loop pattern that extends in multiple dimensions rather than a straight line, allowing the wire to route around protrusions in the vertical and lateral directions. This multi-dimensional routing enables reliable electrical connectivity while maintaining compact horizontal package footprint.
Solution Approach 2:
The wire path is segmented into multiple portions (first portion extending away from bonding pad, second portion approaching bonding pad) that are spatially separated to avoid contact with protrusions. This segmentation allows the wire to navigate around obstacles while maintaining electrical connectivity.
2Productivity
If more semiconductor chips are stacked in the same region to increase integration density, then the integration density increases, but the risk of short-circuits between wires and protrusions increases
Solution Approach 1:
By routing the wire in a folded loop configuration that utilizes vertical and lateral spacing, the wire operates in additional spatial dimensions to maintain safe distances from protrusions on stacked chips, enabling higher integration density without increasing short-circuit risk.
Solution Approach 2:
The folded loop wire configuration acts as an intermediary pathway that mediates between the bonding pad and the chip, providing a routed connection that avoids direct contact with protrusions while maintaining electrical connectivity.
3Reliability
If the wire is configured as a folded loop to prevent contact with protrusions, then the reliability improves by preventing short-circuits, but the wire length and complexity increase
Solution Approach 1:
Instead of making the protrusion retractable or moving the bonding pad, the solution inverts the approach by making the wire path flexible and adaptive, configuring it in a folded loop that automatically routes around fixed protrusions, thereby maintaining simplicity in component design while achieving reliability.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.