Semiconductor Package Underfill Layout for Wire Sweep Prevention

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Solution Overview

Problem

In semiconductor packages, wire sweeping failures during the molding process and surface contamination of bond fingers due to underfill solution fumes lead to poor reliability and defects in the wire bonding process.

Innovation Solution

A semiconductor package design featuring a package substrate with dam structures surrounding substrate pads, where the second underfill member covers bonding wires and substrate pad surfaces, preventing wire sweeping and contamination, and the underfill process is performed after bonding wire formation to minimize defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bonding is performed after underfill process, then bonding wire may be contaminated by underfill solution fumes causing defects, but performing wire bonding before underfill process may cause bond finger surface contamination

Engineering Contradiction:
Improvewire bonding reliabilityVSAvoidbond finger contamination
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The substrate surface is divided into different regions: a first region for mounting the first semiconductor chip and a second region surrounding the first region for forming bond fingers. This spatial segmentation allows wire bonding to be performed in the second region without contamination from underfill solution applied to the first region, while preventing bond finger contamination.

Inventive Principle:
Principle #1Segmentation

2Strength

If molding process is performed with heat and pressure, then bonding wires may be torn from bond finger due to wire sweeping failure, but without proper molding the package lacks mechanical protection

Engineering Contradiction:
Improvemechanical protectionVSAvoidwire bonding integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The substrate has different surface characteristics in different regions: the first region has a first surface property suitable for chip mounting, while the second region has a second surface property that prevents bonding wire adhesion during molding. This local quality differentiation allows the molding compound to protect the package mechanically while not adhering to or tearing the bonding wires in the second region.

Inventive Principle:
Principle #3Local quality

3Reliability

If dam structures are added to prevent wire sweeping and contamination, then manufacturing complexity increases, but without dam structures reliability deteriorates

Engineering Contradiction:
Improvepackage reliabilityVSAvoidsubstrate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate serves multiple functions: it provides mechanical support, electrical connections, and process control all in one component. By designing the substrate with distinct first and second regions having different surface properties, it simultaneously prevents bond finger contamination, protects bonding wires during molding, and eliminates the need for separate dam structures, thereby reducing overall device complexity while maintaining high reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250006720A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2025.01.02 SAMSUNG ELECTRONICS CO LTD
  • US20250006720A1 patent drawing
  • US20250006720A1 patent drawing
  • US20250006720A1 patent drawing

AI summary

A semiconductor package includes a package substrate, at least one dam structure extending on the package substrate to surround substrate pads and defining an inner space that accommodates the substrate pads on the package substrate, a first semiconductor on the package substrate, a second semiconductor chip attached to the first semiconductor chip by an adhesive film, bonding wires electrically connecting chip pads of the second semiconductor chip to the substrate pads of the package substrate, a first underfill member filling a gap between the package substrate and the first semiconductor chip, a second underfill member filling the inner space of the at least one dam structure, and a molding member covering the first semiconductor chip, the second semiconductor chip and the first and second underfill members on the package substrate.