Semiconductor Package Layout for Shorter Wires and Lower Warpage
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Solution Overview
Problem
Existing semiconductor packages face issues with bonding wire damage during manufacturing and require significant space for wiring, leading to increased size and warpage due to thermal stress differences.
Innovation Solution
A semiconductor package design featuring a first substrate with semiconductor chips connected via conductive bumps and wires to a second substrate, utilizing a molding layer to reduce wire length and minimize exposure, and a method of manufacturing that includes forming a flat molding surface to facilitate closer chip placement and reduce thermal stress-induced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect semiconductor chips and substrate, then electrical connection is achieved, but wires may be damaged during manufacturing process
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the semiconductor chips and the substrate. This interposer substrate provides a protected pathway for electrical connections, replacing direct wire bonding that is susceptible to damage. The interposer substrate acts as a mediator that distributes and protects the electrical connection paths, reducing the risk of wire damage during manufacturing processes.
2Ease of operation
If wiring space is increased to accommodate connections, then electrical connectivity is improved, but overall package size increases
Solution Approach 1:
The patent transitions from a planar wiring arrangement to a three-dimensional stacked architecture. Multiple semiconductor chips are vertically stacked and connected through the interposer substrate, utilizing the vertical dimension (Z-axis) for inter-chip connections. This dimensional change allows electrical connectivity between chips without requiring additional horizontal space, thereby reducing the overall package footprint while maintaining full wiring capability.
3Volume of moving object
If multiple semiconductor chips are placed closer together, then package size is reduced, but thermal stress differences cause warpage
Solution Approach 1:
The patent modifies the structural parameters by introducing the interposer substrate with specific mechanical and thermal properties that serve as a compliance layer. This interposer substrate is designed with parameters (material composition, thickness, elastic modulus) that allow it to absorb and distribute thermal stress differences between closely spaced semiconductor chips and the substrate, preventing warpage while enabling compact packaging.
4Reliability
If wire length is reduced, then manufacturing reliability improves, but wiring flexibility decreases
Solution Approach 1:
The patent segments the electrical connection path into multiple shorter sections: connections from each semiconductor chip to the interposer substrate, and from the interposer substrate to the final substrate. This segmentation replaces a single long wire with multiple shorter connection segments, improving reliability by reducing the length of each individual wire while the interposer substrate provides flexible routing capabilities to maintain wiring adaptability.
Data Source
AI summary
A semiconductor package includes a first substrate including a first interconnection structure, a first semiconductor chip, a second semiconductor chip, a second substrate, a molding layer between the first substrate and the second substrate, a plurality of conductive bumps that electrically connect the first interconnection structure to a first chip pad on a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip, and a plurality of conductive wires that electrically connect the first interconnection structure to a second chip pad on a second surface of the second semiconductor chip that is opposite to the first surface of the second semiconductor chip.