Semiconductor Package Layout Without Conductive Bumps
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Solution Overview
Problem
In package-on-package technology, the use of conductive bumps in semiconductor packages increases device thickness, complicates manufacturing processes, and deteriorates heat dissipation characteristics, while also reducing reliability due to the formation of intermetallic compounds.
Innovation Solution
A semiconductor package design that eliminates conductive bumps by using a stacked structure with redistribution wiring layers and a semiconductor substrate, where memory and logic semiconductor chips are electrically connected through redistribution wiring layers, reducing manufacturing processes and eliminating the need for conductive connection wiring and high-density circuit boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive bumps are used to electrically connect stacked semiconductor packages, then electrical connection is achieved, but device thickness increases and manufacturing processes become complicated
Solution Approach 1:
The patent removes conductive bumps from the stacked package structure and replaces them with redistribution wiring layers that provide electrical connections through planar traces on substrate surfaces. This extraction of the bump component simplifies manufacturing by eliminating bump formation processes while maintaining electrical connectivity through alternative wiring paths.
Solution Approach 2:
The patent introduces redistribution wiring layers as intermediary elements between stacked semiconductor packages. These wiring layers act as mediators that establish electrical connections without requiring direct physical contact through conductive bumps, thereby simplifying the connection mechanism and reducing manufacturing complexity.
2Reliability
If conductive bumps are used to electrically connect semiconductor packages, then electrical connection is achieved, but device thickness increases
Solution Approach 1:
The patent extracts conductive bumps from the package structure and replaces them with thin redistribution wiring layers. This removal of bulky bump components significantly reduces the overall device thickness while preserving electrical connection functionality through planar wiring implementations.
3Reliability
If conductive bumps are used to electrically connect semiconductor packages, then electrical connection is achieved, but heat dissipation characteristics deteriorate
Solution Approach 1:
The patent removes conductive bumps which are poor thermal conductors and replaces them with redistribution wiring layers that provide superior heat dissipation pathways. This extraction of thermally inadequate components and replacement with thermally efficient wiring structures improves overall heat dissipation characteristics.
4Reliability
If conductive bumps are used to electrically connect semiconductor packages, then electrical connection is achieved, but intermetallic compound formation increases and reliability decreases
Solution Approach 1:
The patent extracts conductive bumps from the package structure, thereby eliminating the source of intermetallic compound formation. By removing these bump components that generate harmful intermetallic compounds during thermal cycling and operation, the patent improves long-term reliability without requiring alternative connection mechanisms.
Solution Approach 2:
The patent converts the harmful effect of intermetallic compound formation by eliminating the bump structure that causes it. The redistribution wiring layers provide a connection method that avoids the chemical reactions and material degradation associated with intermetallic compound formation in conductive bumps.
5Reliability
If embedded trace substrate is used to electrically connect conductive bumps and redistribution wiring layer, then electrical connection is achieved, but manufacturing processes are added
Solution Approach 1:
The patent merges the functions of embedded trace substrate, conductive bumps, and redistribution wiring layers into a single integrated redistribution wiring layer structure. This consolidation eliminates the need for separate embedded trace substrates and reduces the total number of manufacturing processes required to achieve electrical connections.
Data Source
AI summary
A semiconductor package includes a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface, a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer, a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires, and a semiconductor substrate disposed on an upper surface of the third redistribution wire layer, the semiconductor substrate including at least one memory semiconductor chip electrically connected to the fourth redistribution wires.