Semiconductor Package Assembly Without TSVs or Substrate Cavities
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Solution Overview
Problem
Existing semiconductor packaging technologies, such as Chip-on-Wafer-on-Substrate (CoWoS) and Embedded Multi-Die Interconnect Bridge (EMIB), face challenges with complex substrate fabrication processes, difficulty in controlling flatness and positioning accuracy of silicon bridges, and high costs associated with Through Silicon Vias (TSVs, limiting their widespread adoption.
Innovation Solution
A semiconductor packaging method that forms an external connection device and an interconnection device on a carrier, electrically connects semiconductor devices to these devices, and encapsulates them with a molding layer without requiring substrate cavities or TSVs, simplifying the process and reducing costs by eliminating pre-molding and carrier transfer operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If EMIB packaging technology is used to achieve high-density electrical interconnections, then interconnection density is improved, but substrate fabrication process complexity increases
Solution Approach 1:
The packaging structure is divided into independent modules: carrier, interconnection device, and molding layer. Each component can be fabricated and prepared separately, then assembled together. The interconnection device is a standalone component that can be manufactured independently on the carrier, eliminating the need for complex substrate cavity formation and embedding processes.
Solution Approach 2:
The invention extracts the interconnection function from the substrate and implements it through a separate interconnection device. This device includes connection regions that can be electrically connected to semiconductor devices without requiring substrate cavities or Through Silicon Vias (TSVs), thereby simplifying the substrate fabrication process while maintaining high interconnection density.
2Quantity of substance
If silicon bridge is embedded in substrate to achieve high-density interconnections, then interconnection capability is improved, but positioning accuracy control becomes difficult
Solution Approach 1:
The interconnection device is prepared in advance on the carrier with pre-formed connection regions and conductive structures. The semiconductor devices are then mounted and electrically connected to these pre-positioned connection regions. This preliminary preparation of connection points on the carrier eliminates the need for complex real-time positioning during embedding, significantly improving positioning accuracy.
3Quantity of substance
If CoWoS packaging technology is used to achieve high-density interconnections, then interconnection density is improved, but production cost increases
Solution Approach 1:
The invention uses a carrier that can be fabricated using standard PCB or ceramic substrate processes, which are more cost-effective than the specialized substrate requirements for CoWoS and EMIB packages. The carrier serves as a disposable or reusable platform that simplifies the overall manufacturing process and reduces production costs while achieving the same interconnection density goals.
4Reliability
If TSVs are used in CoWoS package to achieve high-density interconnections, then electrical connection capability is improved, but technological requirements and cost increase
Solution Approach 1:
The invention extracts the vertical electrical connection function from TSVs and implements it through the interconnection device's conductive structures and bonding layers. This approach achieves the same electrical connection capability without requiring high-aspect-ratio TSV holes, reducing the technological complexity and manufacturing difficulty while maintaining reliable electrical connections.
Data Source
AI summary
Provided are a semiconductor packaging method, a semiconductor assembly component and an electronic device made using the method. The method comprises: forming an external connection device on one side of the carrier; attaching an interconnection device to the carrier on the same side of the carrier; electrically connecting an active surface of a first semiconductor device to the external connection device and the interconnection device; electrically connecting an active surface of a second semiconductor device to at least the interconnection device; and forming a molding layer. The semiconductor packaging method is advantageous because it does not require forming a cavity in the substrate and/or TSVs. Further, pre-molding and carrier transfer operations are not required because the molding process is carried out only once. As a result, simplification of the fabrication process for high-density interconnect packaging and reduction of associated costs are realized