Semiconductor Package Layout Without Underfill for Faster Chip Signals
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compact size, low manufacturing cost, and enhanced electrical characteristics, particularly in integrating multiple semiconductor chips with efficient signal delivery and mechanical strength.
Innovation Solution
A semiconductor package design featuring a lower and upper substrate with multiple semiconductor chips, a reinforcing structure, and a molding layer that covers the inner sidewall of the reinforcing structure, top surfaces of the substrates, and chip sidewalls, eliminating the need for a separate under-fill layer to minimize horizontal distance and enhance mechanical strength and signal delivery speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a traditional under-fill layer is used between substrates and chips, then mechanical strength is improved, but package size increases and electrical characteristics deteriorate
Solution Approach 1:
The molding layer is designed to simultaneously perform multiple functions: it provides mechanical reinforcement by covering the inner sidewall of the reinforcing structure, encapsulates the chips and substrates, and eliminates the need for a separate under-fill layer. This merging of functions reduces the overall package size while maintaining structural integrity.
Solution Approach 2:
The molding layer serves as a multi-functional component that combines the structural support previously provided by under-fill layers with the encapsulation function. By making the molding layer universal, the design eliminates redundant components and reduces horizontal distance between chips, improving both electrical characteristics and package compactness.
2Adaptability or versatility
If multiple semiconductor chips are integrated horizontally, then functionality is improved, but signal delivery speed deteriorates due to increased horizontal distance
Solution Approach 1:
The patent transitions from traditional horizontal chip arrangement to a vertical stacking configuration where chips are arranged in multiple layers. This dimensional change reduces the horizontal distance between chips while maintaining high integration, thereby improving signal delivery speed without sacrificing functionality.
Solution Approach 2:
The design implements a nested structure where multiple chip layers are vertically stacked within the package, with each layer containing chips. This nesting approach allows multiple chips to be integrated in a compact vertical space, reducing the horizontal footprint and signal path length compared to traditional horizontal arrangements.
3Volume of moving object
If package size is reduced for compact applications, then portability is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The reinforcing structure is formed on the substrate before chip mounting, creating a pre-defined alignment reference. The molding layer is then formed to cover the inner sidewall of this reinforcing structure, providing a precise geometric constraint that guides subsequent chip placement and bonding. This preliminary structuring simplifies alignment precision requirements during manufacturing while enabling compact package design.
Data Source
AI summary
A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.