Semiconductor package with improved reliability
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Solution Overview
Problem
The reliability of wafer-level chip-scale packages (WLCSP) is challenging due to the dissimilar properties between the chip and board, requiring improved packaging methods that are both reliable and cost-effective.
Innovation Solution
A semiconductor package design featuring a semiconductor die with a redistribution layer (RDL) and molding compound encapsulation, along with an interconnect substrate that includes first and second connecting elements, where the molding compound thickness is less than the height of the first connecting elements, allowing exposure for further connection, and a two-layer interconnect substrate with plated through holes for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If WLCSP packaging is used to minimize package size and eliminate package substrate, then cost is reduced and thermal performance is improved, but reliability becomes challenging due to dissimilar properties between chip and board
Solution Approach 1:
The patent introduces an interconnect substrate as an intermediary component between the semiconductor die and the board. This substrate includes connecting elements that interface with both the die and the board, acting as a mediator that bridges the dissimilar properties between chip and board. The interconnect substrate provides a transition layer that manages the mechanical and electrical interfaces, thereby improving reliability without significantly increasing overall package size.
Solution Approach 2:
The patent segments the packaging structure into distinct functional components: the semiconductor die, the molding compound encapsulation, the interconnect substrate with connecting elements, and the board interface. This segmentation allows each component to be optimized independently for its specific function while managing the complexity through modular design. The connecting elements are arranged in arrays that can be independently formed and tested.
2Adaptability or versatility
If the number of semiconductor devices per wafer area is increased to achieve higher-function devices, then device functionality is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent merges multiple functions into the interconnect substrate: it provides electrical interconnection, mechanical support, and interface management between the die and board. The molding compound simultaneously provides encapsulation, structural support, and stress management. This functional merging reduces the number of separate manufacturing steps and components, thereby easing manufacturing complexity while maintaining high device functionality.
Solution Approach 2:
The interconnect substrate is designed with universal functionality to handle multiple roles: electrical connection through connecting elements, mechanical support for the die, stress distribution, and interface compatibility with different board types. This multi-functionality allows the same basic structure to support various device configurations and functionalities without requiring fundamentally different manufacturing approaches.
3Ease of operation
If molding compound thickness is reduced to expose connecting elements for further connection, then interconnect accessibility is improved, but structural protection is reduced
Solution Approach 1:
The patent applies local quality by varying the molding compound thickness in different regions. The molding compound is thicker in areas where structural protection is needed and thinner in areas where connecting elements need to be accessed. This localized thickness variation allows the package to simultaneously provide adequate structural protection while exposing connecting elements for interconnection operations.
Solution Approach 2:
The molding compound partially covers the connecting elements rather than completely encapsulating them. This partial action provides sufficient structural protection and environmental sealing while leaving the upper portions of the connecting elements exposed for further connection operations. The degree of coverage is optimized to balance protection and accessibility requirements.
Data Source
AI summary
A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.