Semiconductor Packaging Antenna Integration via Conductive Columns
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges such as chip warpage, overheating, and reduced bonding strength due to material expansion and contraction, leading to larger PCB areas and reduced product reliability, especially in fan-out wafer-level packaging (FOWLP) with radio frequency antennas.
Innovation Solution
A semiconductor packaging structure with an antenna assembly that includes a substrate with via holes, a rewiring layer, metal bumps, a semiconductor chip, a conductive column, a bottom filling layer, and a polymer layer, where the antenna assembly is electrically connected to the metal bumps through the conductive column and rewiring layer, using a quartz or sapphire substrate for improved heat conductivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the antenna is directly laid out on the PCB, then the antenna function is achieved, but the PCB area and entire packaging structure area become larger
Solution Approach 1:
The patent combines the antenna with the semiconductor chip packaging structure by integrating the antenna assembly into the packaging substrate. The antenna is formed on the packaging substrate and electrically connected to the radio frequency chip through conductive structures, merging the antenna function with the packaging structure to reduce overall area while maintaining antenna functionality.
2Productivity
If fan-out wafer-level packaging (FOWLP) technology is used for miniaturization and high integration, then packaging density is improved, but chip warpage and bonding strength problems occur due to material expansion and contraction
Solution Approach 1:
The patent changes the material parameter by selecting a packaging substrate material with thermal expansion coefficient matched to the semiconductor chip. This parameter adjustment reduces thermal stress and mechanical stress during temperature cycles, thereby reducing chip warpage and maintaining bonding strength while achieving high packaging density.
3Ease of manufacture
If plastic material is used for packaging, then manufacturing cost is reduced, but heat conductivity is poor causing overheating
Solution Approach 1:
The patent uses a composite material structure where the packaging substrate incorporates materials with good thermal conductivity. The substrate may include metal layers or thermally conductive fillers combined with polymer matrices, creating a composite that maintains low cost while significantly improving heat dissipation performance compared to pure plastic materials.
4Area of stationary object
If the antenna assembly is integrated into the packaging structure, then PCB area is reduced, but the packaging process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the antenna structure on the packaging substrate before chip mounting. The antenna pattern is created and electrical connections are established in advance, so that when the chip is later attached and wire-bonded or bump-connected, the antenna integration is already in place, simplifying the overall packaging process despite the added functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances bonding strength, reduces chip warpage, and improves heat dissipation, resulting in a more reliable and compact packaging structure suitable for high-density integration and mass production, while minimizing the impact of external factors like water vapor.
Implementation Method 1
a conductive column, filling in the at least one via hole
Implementation Method 2
using a quartz or sapphire substrate for improved heat conductivity and stability
Data Source
AI summary
The present application provides a semiconductor packaging structure with an antenna assembly, including: a substrate with through-substrate-via holes; a rewiring layer, located on the substrate; metal bumps, located on and electrically connected to the rewiring layer; a semiconductor chip, located on a surface of the rewiring layer and electrically connected to the rewiring layer; a conductive column, filling in the via hole; a bottom filling layer filling up a gap between the semiconductor chip and the rewiring layer; a polymer layer surrounding the metal bumps and the semiconductor chip; and an antenna assembly, which is electrically connected to one metal bump through the conductive column and the rewiring layer. By using the foregoing solution, the rewiring layer and the metal bumps facilitate proper packaging design.