Semiconductor Packaging Adhesion via Cavity-Through Hole Accommodating Space
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Solution Overview
Problem
Conventional semiconductor packaging structures face poor adhesion between the sealing layer and the substrate, leading to reduced sealability and increased manufacturing costs due to the need for plasma cleaning treatments in a vacuum environment.
Innovation Solution
A semiconductor packaging structure with a substrate having an effective region and a dummy region, where the wiring layer is formed with cavities and a mask layer with through holes that cooperate to create an accommodating space, allowing an engaging element in the sealing layer to fill and adhere to the substrate, enhancing adhesion and sealability without the need for plasma cleaning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plasma cleaning treatment is applied to improve adhesion between sealing layer and substrate, then sealability is improved, but manufacturing cost increases due to vacuum equipment requirements
Solution Approach 1:
The patent extracts the plasma cleaning step from the manufacturing process by replacing it with a chemical treatment applied directly to the substrate surface. This removes the need for vacuum equipment while achieving the same adhesion improvement, thereby resolving the contradiction between improved sealability and reduced manufacturing cost
Solution Approach 2:
The patent uses a disposable chemical treatment solution instead of expensive vacuum equipment. The chemical treatment can be applied using simple coating or dipping methods without requiring costly vacuum chambers, thus achieving adhesion improvement at lower manufacturing cost
2Device complexity
If sealing layer is applied directly to substrate to reduce manufacturing complexity, then device complexity is reduced, but adhesion between sealing layer and substrate is insufficient leading to poor sealability
Solution Approach 1:
The patent applies a preliminary chemical treatment to the substrate surface before applying the sealing layer. This preliminary action modifies the substrate surface properties to enhance adhesion, allowing direct application of the sealing layer without complex intermediate steps, thus resolving the contradiction between manufacturing simplicity and adhesion quality
Solution Approach 2:
The patent changes the surface parameters of the substrate through chemical treatment, such as surface energy, roughness, or chemical composition. This parameter modification enables the sealing layer to adhere properly to the substrate directly, achieving good adhesion without increasing manufacturing process complexity
Data Source
AI summary
A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.