Semiconductor Packaging Structure with Conductive Post and Direct Bonding
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Solution Overview
Problem
Current semiconductor packaging structures are complex and hinder high-speed, small-volume interconnection between chips, with existing solutions either being costly due to high interposer costs or resulting in long transmission paths when using bridges for chip connections.
Innovation Solution
A packaging structure and method that eliminates the need for bridges by using a conductive post and strategically arranged bonding regions on chips to directly connect chips, optimizing the packaging structure for faster communication and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon bridge is used to connect chips, then interconnection between chips is achieved, but the packaging structure becomes complex and transmission path is long
Solution Approach 1:
The patent extracts and eliminates the silicon bridge component from the packaging structure. By directly bonding the second chip to the first chip's bonding region, the intermediary bridge is removed, simplifying the packaging structure while maintaining chip interconnection functionality
Solution Approach 2:
The patent segments the chip interconnection function into direct bonding regions on each chip, eliminating the need for a separate bridge component. The first chip has a first bonding region for the chipset and a second bonding region for the second chip, enabling direct stacking and connection
2Reliability
If a silicon bridge is used to connect chips, then interconnection is achieved, but communication speed is reduced due to long transmission path
Solution Approach 1:
By removing the silicon bridge from the interconnection path, the transmission distance between chips is significantly reduced. The direct bonding configuration eliminates the additional transmission path through the bridge, thereby improving communication speed
Solution Approach 2:
The patent transitions from a lateral connection approach (using bridges) to a vertical stacking approach. The second chip is bonded directly to the first chip in the vertical dimension, shortening the transmission path and improving signal speed
3Reliability
If an interposer is used to connect chips, then chip interconnection is achieved, but packaging cost increases
Solution Approach 1:
The patent extracts and eliminates the interposer component from the packaging structure. By implementing direct chip-to-chip bonding through exposed bonding regions, the expensive interposer is removed, reducing overall packaging cost while maintaining interconnection functionality
Solution Approach 2:
The patent replaces expensive, complex interposer structures with simpler, more cost-effective direct bonding solutions. The bonding regions are designed to be self-contained on each chip, eliminating the need for costly intermediary substrates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the packaging structure, shortens transmission paths, and enhances communication speeds between chips, thereby improving overall packaging performance.
Implementation Method 1
a conductive post, arranged in the fourth bonding region, an end of the conductive post facing away from the second chip is bonded to the substrate
Implementation Method 2
the first surface includes a first bonding region configured to bond to a chipset and a second bonding region configured to bond to a second chip
Data Source
AI summary
This disclosure relates to a packaging structure and a packaging method. The structure includes: a substrate; a first chip, including a first surface and a second surface opposite to each other; a second chip, including a third surface, where the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip. The chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip.