Semiconductor Packaging Containers for Bonding Strength
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Solution Overview
Problem
Conventional semiconductor packaging structures require multiple alignment steps, leading to increased manufacturing time and cost, and suffer from poor bonding between redistribution circuit layers and dielectric layers, causing the redistribution circuit layers to peel off during subsequent processes.
Innovation Solution
A semiconductor packaging structure where redistribution circuit layers are partially or totally embedded within containers defined in the dielectric layer, increasing the bonding surface area and using a method that involves forming containers in the dielectric layer to expose connection pads and electrically connecting redistribution circuit layers with these pads, reducing the need for additional alignment steps and enhancing bonding force.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple alignment steps are used to form openings and redistribution circuit layers, then positioning accuracy is improved, but manufacturing time and cost increase
Solution Approach 1:
The dielectric layer is pre-formed with containers that have side walls before the redistribution circuit layers are deposited. This preliminary structuring eliminates the need for subsequent alignment steps to form openings, as the containers are already in their final positions and configurations, thereby reducing manufacturing time while maintaining positioning accuracy.
Solution Approach 2:
The dielectric layer is segmented into multiple containers with side walls that are formed separately and then integrated. This segmentation allows each container to be independently formed and positioned, eliminating the need for complex alignment steps to create openings through a continuous dielectric layer, thus reducing manufacturing complexity and time.
2Ease of manufacture
If redistribution circuit layers are stacked on the dielectric layer with only one surface in contact, then manufacturing process is simplified, but bonding force decreases causing peeling
Solution Approach 1:
The containers in the dielectric layer are given three-dimensional structures with side walls that extend vertically. When redistribution circuit layers are filled into these containers, they contact not only the top surface but also the side walls of the containers, transforming a two-dimensional bonding interface into a three-dimensional bonding structure. This increases the bonding surface area and strength without complicating the manufacturing process.
Solution Approach 2:
The redistribution circuit layers are nested within the containers formed in the dielectric layer. The containers act as receptacles that contain and secure the circuit layers, providing mechanical support and enhanced bonding through the container walls. This nesting structure prevents peeling while maintaining manufacturing simplicity.
Data Source
AI summary
A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.