Semiconductor Packaging Structure with Direct Metal Layer Connections
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Solution Overview
Problem
Current packaging structures for semiconductor chips, particularly in wafer-level chip size packaging (WLCSP), lack versatility and efficiency in integrating electrical connections and solder bumps, leading to increased complexity and cost in the fabrication process.
Innovation Solution
A packaging structure featuring a chip with a compatible pad, an intermediate metal layer, and a redistribution metal layer that directly connects with the solder bump, allowing for various connection shapes (concave, "-", and "T" shapes) to stabilize and increase the number of solder bumps, while simplifying the fabrication process by eliminating the need for additional metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures with multiple metal layers are used, then electrical connections can be established, but the fabrication process becomes more complex and costly
Solution Approach 1:
The patent removes the complex multi-layer metal structure and replaces it with a simplified design using only an intermediate metal layer and redistribution metal layer that directly connect to solder bumps, eliminating unnecessary intermediate layers while maintaining electrical connection functionality
Solution Approach 2:
Instead of building complex multi-layer metal structures from the bottom up, the patent inverts the approach by using a flat substrate with solder bumps that directly connect to simplified metal layers, reducing fabrication complexity while achieving the same electrical connection purpose
2Productivity
If the redistribution metal layer area is reduced, then more solder bumps can be accommodated, but the electrical connection stability may be compromised
Solution Approach 1:
The patent transitions from planar metal layer connections to three-dimensional solder bump connections, where vertical connections through the substrate allow for more compact routing and increased bump density without compromising connection integrity
Solution Approach 2:
The patent changes the connection geometry from extended planar metal traces to concentrated vertical solder bump connections, altering the dimensional parameters to achieve both compact area usage and stable electrical connections
Data Source
AI summary
The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.