Semiconductor Packaging with Dual-Layer EMI Shielding Coverage

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Solution Overview

Problem

Existing semiconductor packaging structures face challenges with inhomogeneous magnetic field shielding layers due to uneven thickness and poor edge coverage, leading to inadequate electromagnetic interference shielding performance.

Innovation Solution

A dual-layer shielding structure is formed by a first shielding layer covering non-functional surfaces and sidewalls, followed by a second shielding layer to address uneven thickness and edge coverage issues, enhancing overall shielding effectiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single magnetic field shielding layer is provided on semiconductor packaging structure, then electromagnetic shielding is implemented, but the shielding layer has inhomogeneous thickness and poor edge coverage leading to inadequate shielding performance

Engineering Contradiction:
Improveelectromagnetic shielding performanceVSAvoidshielding layer thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The shielding structure is divided into multiple independent shielding layers instead of using a single layer. Each shielding layer can be formed and controlled separately, allowing for better thickness uniformity and coverage. The first shielding layer is formed to cover initial areas, then a second shielding layer is formed to cover remaining areas, with each layer optimized for its specific function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution transitions from a single-layer approach to a multi-layer approach, adding the dimension of layer stacking. This allows the shielding structure to achieve comprehensive coverage by forming layers at different stages, with the first layer addressing certain areas and the second layer addressing other areas, thereby solving the edge coverage and thickness uniformity problems.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If electromagnetic shielding is added to semiconductor packaging, then electromagnetic interference protection is improved, but the packaging structure complexity increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidpackaging structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The shielding layers are integrated with the existing packaging structure rather than being added as separate external components. The first and second shielding layers are formed as part of the packaging process, combining the shielding function with the structural packaging layers, thereby reducing overall complexity while maintaining effective electromagnetic interference protection.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250372532A1Packaging structure
Publication Date: 2025.12.04 NANTONG TONGFU MICROELECTRONICS CO LTD
  • US20250372532A1 patent drawing
  • US20250372532A1 patent drawing
  • US20250372532A1 patent drawing

AI summary

A packaging structure includes semiconductor chips embedded in a plastic encapsulation layer and each including a functional surface and a non-functional surface; soldering pads on functional surfaces of the semiconductor chips; a metal bump on each soldering pad; a first plastic encapsulation layer on the functional surfaces of the semiconductor chips covering sidewalls of metal bumps and exposing top surfaces of the metal bumps, a first shielding layer and a second shielding layer between the semiconductor chips and the plastic encapsulation layers; and an external contact structure connected to each metal bump on the first plastic encapsulation layer. The first shielding layer covers the non-functional surfaces and the sidewalls of the semiconductor chips, and side surfaces of the first plastic encapsulation layer. The second shielding layer covers a portion of the first shielding layer on the non-functional surfaces and the sidewalls of the semiconductor chips.