Semiconductor Packaging Using Interposer and Carrier Process

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Solution Overview

Problem

The semiconductor industry faces challenges in developing improved packaging structures and methods for semiconductor devices that require smaller form factors and higher integration density, while maintaining reliability and reducing manufacturing costs.

Innovation Solution

The proposed solution involves novel packaging methods where multiple dies are packaged both vertically and horizontally in a single package using interposers with through-substrate vias (TSVs) and a carrier-based process, eliminating the need for a substrate, which allows for reduced package thickness, lower costs, and increased integration density through chip redistribution and molding technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If traditional substrate-based packaging is used, then structural support and electrical connections are provided, but package thickness is increased and thermal expansion mismatches occur

Engineering Contradiction:
Improvepackage thicknessVSAvoidthermal expansion match
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent removes the traditional substrate from the packaging structure entirely. Instead of using a substrate to provide structural support and electrical connections, the invention uses interposers with through-substrate vias that are directly bonded to carrier plates, eliminating the substrate-related thermal expansion mismatch problem while reducing package thickness

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces interposers as intermediary components between the carrier plate and the semiconductor dies. These interposers provide the necessary electrical connections and structural support without being a traditional substrate, thereby mediating between the carrier plate and dies while avoiding thermal expansion issues

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If integration density is increased, then more components are integrated into a given area, but package size must be reduced

Engineering Contradiction:
Improveintegration densityVSAvoidpackage size
Core Design Contradiction:
ProductivityVSVolume of moving object

Solution Approach 1:

The patent transitions from two-dimensional planar packaging to three-dimensional vertical packaging by stacking multiple semiconductor dies vertically on interposers. This dimensional change allows higher integration density within a smaller footprint, as components are arranged in multiple layers rather than a single plane

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where semiconductor dies are mounted on interposers, which are in turn mounted on carrier plates. Multiple dies are stacked vertically, creating a nested arrangement that maximizes component density within the package volume while maintaining a compact overall size

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If multiple dies are packaged vertically and horizontally, then integration density increases, but manufacturing complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the packaging process into distinct segments: carrier plate preparation, interposer bonding to carrier, die bonding to interposers, and underfill application. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing process despite the complex final structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-bonding interposers to carrier plates before mounting the semiconductor dies. This preliminary structuring simplifies subsequent die attachment processes and enables better control over alignment and positioning, reducing manufacturing complexity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9299682B2Packaging methods for semiconductor devices
Publication Date: 2016.03.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9299682B2 patent drawing
  • US9299682B2 patent drawing
  • US9299682B2 patent drawing

AI summary

Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.