Semiconductor Packaging Method Eliminates Interposer
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Solution Overview
Problem
Conventional semiconductor packaging methods with interposers face issues of increased package thickness, delamination, and warpage due to CTE mismatch and poor adhesion between layers, especially when dealing with chips of different dimensions.
Innovation Solution
A semiconductor packaging method that eliminates the interposer by using a two-layer mother chip with a semiconductor layer and an organic layer, where a redistribution layer is embedded in the organic layer to facilitate electrical connections between chips, allowing direct attachment of daughter chips to the mother chip without additional thickness or bumps, thereby reducing overall package thickness and addressing adhesion and warpage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to assemble multi-chip stacked packages with chips of different dimensions, then electrical connections between daughter chip and mother chip can be achieved, but the overall package thickness is increased
Solution Approach 1:
The patent merges the interposer function with the mother chip by integrating a redistribution layer directly into the mother chip structure. The mother chip includes a first chip, a first die attach layer, and a redistribution layer formed on the first die attach layer, eliminating the need for a separate interposer component while maintaining electrical connection functionality between chips of different dimensions.
Solution Approach 2:
The mother chip is designed to perform multiple functions: it serves as both the primary chip carrier and the interposer for redistribution. The redistribution layer is formed directly on the mother chip's die attach layer, allowing the mother chip to handle both signal distribution and mechanical support functions that traditionally required a separate interposer.
2Reliability
If an interposer is used to assemble multi-chip stacked packages, then electrical connections between different dimension chips are enabled, but delamination occurs due to CTE mismatch
Solution Approach 1:
By integrating the redistribution layer directly onto the mother chip's die attach layer rather than using a separate interposer, the patent reduces the number of interfaces between different materials. This merger eliminates the CTE mismatch issue that causes delamination at the interposer-chip interfaces, as there are now fewer distinct material layers with different thermal expansion coefficients.
3Reliability
If an interposer is used to assemble multi-chip stacked packages, then electrical connections are achieved, but package warpage occurs due to poor adhesion between adjacent layers
Solution Approach 1:
The patent combines the interposer functionality into the mother chip structure, reducing the number of separate layers and interfaces. The redistribution layer is formed directly on the mother chip's die attach layer, creating fewer potential sites for adhesion failure and reducing the cumulative effect of thermal stress that causes warpage in multi-layer stacked packages.
4Ease of manufacture
If a conventional interposer structure is used, then two die-attaching layers are required, but the overall package thickness is increased
Solution Approach 1:
The patent merges the functionality of separate die-attaching layers into a single integrated structure. The redistribution layer is formed directly on the first die attach layer of the mother chip, eliminating the need for a second die attach layer on a separate interposer, thereby reducing the overall package thickness while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.