Semiconductor Packaging Jig Structure for Precise Multi-Die Assembly

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Solution Overview

Problem

The integration of multiple semiconductor devices into a single package has become a challenge due to the increasing demand for miniaturization, higher speed, and better electrical performance in electronic devices.

Innovation Solution

The development of a semiconductor package manufacturing process that involves the use of jigs with specific structures to facilitate the assembly and packaging of semiconductor dies and bridges, including the formation of redistribution layers and the application of thermal interface materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple semiconductor devices are integrated into a single package to achieve miniaturization and improved electrical performance, then the electrical performance and transmission loss are improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical performanceVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages: forming redistribution layers on separate substrates, bonding substrates together, and then performing singulation. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while achieving multi-device integration with improved electrical performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar wafer-level processing to three-dimensional package stacking. Multiple semiconductor devices are integrated vertically through substrate bonding rather than horizontally on a single wafer, reducing transmission loss and improving electrical performance while managing integration complexity through spatial reorganization

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If wafer-level processing and packaging are used to improve manufacturing efficiency, then productivity increases, but the manufacturing precision and alignment accuracy decrease

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidalignment accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Redistribution layers and bonding interfaces are prepared in advance on separate substrates before final assembly. Alignment features and bonding pads are pre-positioned with high precision during substrate fabrication, allowing subsequent bonding to proceed rapidly without compromising alignment accuracy, thus maintaining both productivity and manufacturing precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediate substrates with redistribution layers that serve as mediators between the semiconductor devices and the final package. These intermediate layers provide precise alignment references and electrical interconnections, enabling high-precision multi-device integration while maintaining efficient wafer-level processing

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If complex packaging structures are used to achieve better electrical performance and miniaturization, then the electrical performance improves, but the ease of manufacture decreases

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Multiple manufacturing operations are merged into integrated process steps. For example, redistribution layer formation is combined with substrate preparation, and substrate bonding is performed before singulation. This merging reduces the total number of discrete manufacturing steps, simplifying production while achieving complex multi-device integration with improved electrical performance

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding process is designed to be self-aligning through complementary features on the substrates, such as protrusions fitting into recesses or magnetic alignment layers. This self-service mechanism eliminates the need for complex external alignment equipment and procedures, making the manufacturing of complex stacked packages simpler and more robust

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12211818B2Manufacturing method of semiconductor package using jig
Publication Date: 2025.01.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12211818B2 patent drawing
  • US12211818B2 patent drawing
  • US12211818B2 patent drawing

AI summary

A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.