Thin Semiconductor Packaging With Laser-Patterned Vias and Cavities
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Solution Overview
Problem
Conventional semiconductor device packages face limitations in scalability and performance due to the rigidity and planarity of materials used, leading to difficulties in patterning fine features and causing coefficient of thermal expansion mismatches, which result in low die-to-package area ratios and power efficiency.
Innovation Solution
The method involves structuring a silicon substrate with micro-blasting or direct laser patterning to form vias and cavities, followed by the use of pre-structured insulating films with flowable polymer-based dielectric materials to create conductive layers through these features, enabling the formation of thin-form-factor semiconductor device packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic package substrates are used, then ease of manufacture and low manufacturing cost are achieved, but material structuring resolution is insufficient to sustain device scaling
Solution Approach 1:
The patent uses a composite structure combining silicon substrate with organic package substrate. The silicon substrate provides high-precision structuring for TSVs and fine features, while the organic package substrate provides ease of manufacture and cost-effectiveness for the overall package. This composite approach resolves the contradiction by assigning different functional requirements to different materials.
Solution Approach 2:
The patent segments the package structure into distinct functional layers: a silicon substrate layer for high-precision interconnections and TSVs, and an organic package substrate layer for cost-effective manufacturing and packaging. This segmentation allows each layer to optimize for its specific requirements without compromising the other.
2Productivity
If silicon interposers are used, then high-bandwidth density and lower-power chip-to-chip communication are achieved, but formation of features such as through-silicon vias is difficult and costly
Solution Approach 1:
The patent changes the structural parameters of the silicon substrate by forming through-silicon vias (TSVs) with optimized dimensions and arrangements. By carefully controlling via diameter, depth, and spacing, the patent achieves high-bandwidth density while managing the complexity of via formation through standardized process parameters.
Solution Approach 2:
The patent transitions from planar interconnections to three-dimensional vertical interconnections using TSVs. This dimensional change enables high-bandwidth density by utilizing the vertical dimension for signal routing, allowing multiple interconnection layers and higher port densities without proportionally increasing lateral footprint.
3Device complexity
If conventional package structures are used, then manufacturing simplicity is maintained, but coefficient of thermal expansion mismatches result in low die-to-package area ratios and power efficiency
Solution Approach 1:
The patent applies local quality by using different materials with appropriate CTE properties in different regions of the package. The silicon substrate provides low CTE for thermal stability near the die, while the organic package substrate provides appropriate CTE matching in the package body. This localized material selection resolves thermal expansion mismatches while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of semiconductor device packages with improved scalability, reduced thermal mismatch issues, and increased power efficiency by enabling the formation of fine features and efficient interconnections within a smaller footprint.
Implementation Method 1
The pre-structured insulating film comprises a flowable, polymer-based dielectric material... curing the pre-structured insulating film
Data Source
AI summary
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.