Semiconductor Packaging Thermal Management for Memory Reliability
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Solution Overview
Problem
High bandwidth memory dies, such as DRAM, are sensitive to high temperatures used for curing passivation layers, which can lead to increased failure rates and decreased reliability and yield rates of device packages when integrated with logic dies in conventional packaging technologies.
Innovation Solution
A new packaging structure where a logic die is packaged with a high temperature curing passivation layer, while the high bandwidth memory die is not, allowing for a molding compound to directly cover the memory die, thus avoiding temperature-sensitive curing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high temperature curing passivation layer is formed over the logic die, then the passivation and protection function is improved, but the reliability of high bandwidth memory die decreases due to temperature sensitivity
Solution Approach 1:
The patent divides the passivation layer formation into two separate segments: a first passivation layer formed over the logic die requiring high temperature curing, and a second passivation layer formed over the high bandwidth memory die using low temperature curing. This segmentation allows each die type to receive appropriate curing treatment, resolving the contradiction between achieving proper passivation and avoiding thermal damage to temperature-sensitive memory die.
Solution Approach 2:
The patent applies different curing temperature regimes to different locations on the wafer based on the underlying die type. Logic dies receive high temperature curing for their passivation layers, while high bandwidth memory dies receive low temperature curing. This localized quality approach ensures each region receives the appropriate thermal treatment, maintaining passivation effectiveness while protecting temperature-sensitive components.
2Ease of manufacture
If conventional packaging technology with uniform passivation layer is used, then the manufacturing process is simple, but the yield rate decreases due to failure of memory dies during curing
Solution Approach 1:
The patent segments the passivation layer formation process into distinct stages for logic dies and high bandwidth memory dies, with separate curing temperature protocols. Although this increases process complexity compared to uniform treatment, it dramatically improves yield rate by preventing memory die failures during curing, thus resolving the contradiction between manufacturing simplicity and production yield.
3Reliability
If a molding compound is formed directly over the high bandwidth memory die without a passivation layer, then the reliability of memory die is improved by avoiding high temperature curing, but the protection function is reduced
Solution Approach 1:
The patent introduces a second passivation layer as an intermediary protective layer between the molding compound and the high bandwidth memory die. This second passivation layer provides necessary protection and environmental isolation for the memory die while allowing the molding compound to be formed at lower temperatures that do not damage the temperature-sensitive memory die, thus resolving the contradiction between reliability improvement and protection function.
Data Source
AI summary
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.