Semiconductor Packaging With Selective Etch Recessed Conductive Balls
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving efficient vertical integration and reducing area usage, particularly in 3DICs and PoP devices, where residue formation from grinding processes can lead to shorts and current leakage, and high temperature curing is required for molding compounds, which can cause warpage.
Innovation Solution
A novel packaging method involving a substrate with through-substrate vias, conductive balls and bumps, a selective etch process to recess these components, and a redistribution layer (RDL) to prevent residue and reduce thermal budget, allowing for embedded integration without additional interposers and enabling low-cost 3D packaging with improved adhesion and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high temperature curing is used for molding compounds, then adhesion is improved, but warpage increases
Solution Approach 1:
The patent changes the thermal parameter by using a low-temperature curing molding compound (curing at 70-100°C instead of traditional high temperatures). This parameter change resolves the contradiction by achieving adequate adhesion without the high temperatures that cause warpage in stacked semiconductor devices.
2Manufacturing precision
If grinding process is used to remove molding compound, then exposure of conductive balls is achieved, but residue formation causes shorts and current leakage
Solution Approach 1:
The patent replaces the mechanical grinding process with a chemical etch process. The etch selectively removes the molding compound to expose conductive balls and bumps without creating conductive residue, thereby achieving both precise exposure and preventing shorts/current leakage that would result from grinding residue.
Solution Approach 2:
The etch process uses chemical oxidation to selectively remove the molding compound material. This chemical approach provides cleaner removal compared to mechanical grinding, preventing conductive residue formation while exposing the conductive elements.
3Productivity
If multiple interposers are used for vertical integration, then integration density is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the interposer components from the packaging structure. By removing the interposers and directly stacking dies with conductive balls/bumps, the design achieves vertical integration without the added complexity and cost of multiple interposer layers.
Solution Approach 2:
The patent merges the functions of multiple components (substrate, conductive interconnects, and stacking structure) into a simplified integrated architecture. The conductive balls and bumps directly provide both electrical interconnection and mechanical support, eliminating the need for separate interposer structures.
Data Source
AI summary
Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.