Semiconductor Packaging Stress Management via Layered Dielectric and Resin
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Solution Overview
Problem
Conventional semiconductor device packaging methods face issues with inner stress in packaging materials, leading to warpage problems due to inadequate stress distribution.
Innovation Solution
A manufacturing method involving a substrate with a sacrificial layer, a resin layer, and dielectric layers with trenches, where the upper surfaces of the dielectric and resin layers are aligned to form a packaging structure that adjusts stress distribution by using materials with different coefficients of thermal expansion, and incorporating spacer balls for package-on-package structures to mitigate warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures are used, then manufacturing process is simple, but warpage occurs due to inner stress in packaging materials
Solution Approach 1:
The packaging structure is divided into multiple dielectric layers (first dielectric layer, second dielectric layer) with different materials and properties. Each layer serves specific functions: the first dielectric layer provides stress relief, while the second dielectric layer provides planarization. This segmentation allows independent optimization of each layer to address warpage while maintaining overall structural integrity.
Solution Approach 2:
Different regions of the packaging structure use different materials with specific properties tailored to local requirements. The first dielectric layer uses material with specific stress characteristics, while the second dielectric layer uses material optimized for planarization. This local quality approach enables precise control of stress distribution across different areas of the packaging structure.
2Manufacturing precision
If packaging materials with uniform properties are used, then manufacturing is easier, but stress distribution is inadequate leading to warpage
Solution Approach 1:
The packaging structure employs composite materials consisting of multiple dielectric layers with different properties. The first dielectric layer and second dielectric layer are made from different materials selected to provide complementary functions: stress management and surface planarization. This composite approach enables precise control of stress distribution while maintaining manufacturability through standardized layering processes.
3Reliability
If single-layer dielectric structure is used, then device complexity is low, but warpage cannot be effectively controlled
Solution Approach 1:
The single dielectric layer is segmented into multiple functional layers: the first dielectric layer positioned adjacent to the chip for stress relief, and the second dielectric layer positioned above for planarization. This segmentation transforms a simple single-layer structure into a multi-functional layered structure that effectively controls warpage while maintaining reasonable complexity through systematic layer arrangement.
Solution Approach 2:
The solution transitions from a single-layer planar structure to a multi-layer three-dimensional structure with vertical stacking. The first dielectric layer and second dielectric layer are arranged in different vertical positions, creating a layered architecture that provides both stress management and surface planarization functions that cannot be achieved with a single planar layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces warpage in semiconductor devices by managing stress distribution through aligned dielectric and resin layers and spacer balls, enhancing packaging reliability and heat dissipation.
Implementation Method 1
the first chip is separated from the sacrificial layer and the substrate
Implementation Method 2
materials with different coefficients of thermal expansion
Data Source
AI summary
A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, forming a resin layer on the sacrificial layer, disposing first chips on the sacrificial layer, and forming a first dielectric layer having trenches and surrounding the first chips, wherein an upper surface of the first dielectric layer and an upper surface of the resin layer are at a same plane.