Semiconductor Packaging Via Formation Using Laser Drilling

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Solution Overview

Problem

Conventional Through Silicon Via (TSV) die stacking processes are costly due to expensive front-end processes like dual damascene and deep reactive-ion etching, and they face challenges in achieving compact sizes and high performance for handheld consumer electronics.

Innovation Solution

The method involves forming a semiconductor packaging structure with a vertical stacked arrangement of semiconductor packages, each encapsulated in a mold compound, with electrically conductive filled vias extending through the mold portion, using laser drilling and electroplating to create tapered vias that connect the packages, replacing TSV with Through Mold Via (TMV) technology and fanout redistribution layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Through Silicon Via (TSV) technology is used for die stacking, then vertical interconnections and high I/O are achieved, but processing costs increase due to expensive front-end processes

Engineering Contradiction:

Improvevertical interconnection capabilityVSAvoidprocessing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the via formation process from the silicon substrate and relocates it to the mold compound material. Instead of forming vias through the silicon die (TSV), the invention forms vias through the mold compound after packaging, thereby avoiding expensive silicon etching processes while achieving the same vertical interconnection function.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The conventional approach forms vias before packaging (in the silicon substrate). The patent inverts this sequence by forming vias after packaging (in the mold compound), reversing the traditional process flow to achieve cost reduction while maintaining functionality.

Inventive Principle:

Principle #13The other way round (Inversion)

2Manufacturing precision

If dual damascene and deep reactive-ion etching processes are used, then precise via formation is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvevia formation precisionVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent uses mold compound, a relatively inexpensive and easily processable material, instead of silicon substrate for via formation. The mold compound serves as a temporary structure that can be easily drilled and filled, replacing the need for complex silicon processing while achieving the required precision for vertical interconnections.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Adaptability or versatility

If conventional TSV stacking is used, then high I/O capability is achieved, but form factor size increases

Engineering Contradiction:

ImproveI/O capabilityVSAvoidform factor size

Core Design Contradiction:

Adaptability or versatilityVSVolume of moving object

Solution Approach 1:

The patent transitions from planar interconnection to vertical interconnection by forming vias through the mold compound in the vertical dimension. This allows I/O signals to pass through the stacked packages vertically, enabling high I/O capability while maintaining a compact form factor by utilizing the vertical stacking architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces processing costs and enables smaller form factors by using TMV technology, allowing for efficient vertical interconnections and lower processing costs while maintaining high performance.

Implementation Method 1

forming a first via on the mold portion at the first side of the vertical stacked arrangement after the vertical stacked arrangement is formed

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

forming an electrically conductive filled via extending through the mold portion from the first side of the vertical stacked arrangement to the second side of the vertical stacked arrangement by depositing a suitable electrically conductive material in the first via and in the second via

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS10727207B2Semiconductor packaging structure and method of forming the same

Publication Date: 2020.07.28 AGENCY FOR SCI TECH & RES

AI summary

Various embodiments may provide a method of forming a semiconductor packaging structure. The method may include forming a plurality of semiconductor packages, each semiconductor package including a semiconductor die and a mold encapsulation structure. The method may also include arranging the plurality of semiconductor packages to form a vertical stacked arrangement with a mold portion including a plurality of mold encapsulation structures, the mold portion extending from a first side to a second side of the vertical stacked arrangement opposite the first side. The method may additionally include forming a first via on the mold portion at the first side of the vertical stacked arrangement, forming a second via on the mold portion at the second side of the vertical stacked arrangement, and forming an electrically conductive filled via extending through the mold portion from the first side to the second side of the vertical stacked arrangement.