Semiconductor Pad-Over-Active Layout for Lower On-Resistance
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Solution Overview
Problem
The separation of active and pad arrangement regions in semiconductor devices reduces the active region's ratio to the total chip area, making it difficult to lower the on-resistance of semiconductor elements.
Innovation Solution
The active region is expanded to include the region below the pad arrangement region, with a double-layer wiring electrode structure where the pad overlaps the active region, and a single-layer structure where it does not, using an isolation insulating film to connect the layers only in non-overlapping areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the active region and pad arrangement region are separated, then the pad arrangement region can be clearly defined, but the active region's ratio to the total chip area is reduced
Solution Approach 1:
The invention transitions from a planar separation of active and pad regions to a three-dimensional overlapping structure. The pad arrangement region is positioned above the active region in the vertical dimension, allowing both regions to coexist without lateral interference. This dimensional transition enables the active region to extend across the entire chip area while pads are arranged in an overlapping configuration, thereby increasing the active region area ratio without compromising pad definition.
Solution Approach 2:
The invention implements a nested structure where the pad arrangement region is effectively nested above the active region. The projection of the pad arrangement region overlaps with the active region, creating a hierarchical spatial arrangement. This nesting allows the pad structure to be positioned within the vertical space above the active region, enabling both regions to occupy the same lateral footprint while maintaining distinct functional zones.
2Reliability
If the active region area is increased, then the on-resistance can be reduced, but the chip warp at high temperatures increases
Solution Approach 1:
By moving the pad arrangement to an overlapping vertical configuration, the invention allows the active region to expand across the entire chip area, reducing on-resistance. The vertical stacking of pads above the active region prevents lateral expansion that would cause warp, while still achieving full active region coverage through the overlapping dimension.
Solution Approach 2:
The invention applies different structural qualities to different regions: the active region uses a single-layer wiring electrode structure for optimal electrical performance and low on-resistance, while the pad arrangement region uses a double-layer structure for mechanical stability and warp suppression. This local differentiation allows each region to be optimized for its specific function while working together as a unified structure.
Data Source
AI summary
A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.