Semiconductor Pad Alignment via Dummy Mark for Wire Bonding
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Solution Overview
Problem
In semiconductor device manufacturing, the alignment accuracy of wire bonding positions is compromised due to the thickness of semiconductor layers, leading to deviations in opening positions formed during photolithography, which affects the precision of dummy pad detection and subsequent wire bonding.
Innovation Solution
A semiconductor device design featuring a first and second semiconductor layer with overlapping openings and pads, where the second pad has a larger width than its opening, and an alignment mark is formed on the second pad, allowing for accurate detection and alignment despite the thickness of the semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to form openings in thick semiconductor layers, then the openings can be formed through the layer, but the position of the openings deviates from the designed position due to focusing issues
Solution Approach 1:
A dummy pad structure is introduced as an intermediary element between the opening and the actual pad. The dummy pad includes a first region (aligned with the opening) and a second region (extending beyond the opening), which serves as a more accurate alignment reference for image recognition, thereby compensating for the position deviation caused by thick semiconductor layers during photolithography.
Solution Approach 2:
The dummy pad creates a copied or replicated reference structure that is easier to detect and measure. Instead of directly using the opening or the actual pad for alignment, the dummy pad provides a copied reference pattern that enhances the accuracy of position detection and alignment in the wire bonding process.
2Measurement precision
If image recognition is used to detect pad centers for wire bonding alignment, then alignment can be performed, but the detection accuracy is insufficient when semiconductor layers are thick
Solution Approach 1:
The dummy pad acts as an intermediary reference object that improves image recognition accuracy. The first region of the dummy pad aligns with the opening while the second region extends beyond it, creating a distinct pattern that is easier for the image recognition system to detect and measure, thereby achieving more accurate center detection despite the thickness of the semiconductor layer.
Solution Approach 2:
The dummy pad structure creates optical contrast differences that enhance detectability. By having regions with different dimensions (first region aligned with opening, second region extending beyond), the dummy pad creates varying optical patterns that improve the ability of image recognition systems to distinguish and accurately locate the alignment reference points.
3Reliability
If wire bonding is performed based on detected pad positions, then electrical connection is established, but misalignment may occur causing wire contact with opening sides or semiconductor layer surface
Solution Approach 1:
The dummy pad serves as an intermediary alignment reference that improves the accuracy of wire bonding positioning. By using the dummy pad's distinct pattern (with first and second regions) for alignment instead of directly relying on the opening or pad center detection, the system achieves better positioning accuracy, reducing the risk of wire misalignment with opening sides or semiconductor layer surface.
Solution Approach 2:
The dummy pad structure provides a built-in safety margin or cushioning effect. The second region of the dummy pad extends beyond the opening, creating a reference pattern that accounts for potential position deviations. This beforehand design compensates for alignment errors, ensuring that even with some detection variability, the wire bonding remains accurately positioned and avoids contact with opening sides or the semiconductor layer surface.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.