Semiconductor Package Pad Structure for Compact Reliable Interconnects
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing chip size while maintaining reliability and minimizing failure rates, particularly due to limitations in redistribution structures that connect chips to external components.
Innovation Solution
The semiconductor package design incorporates a redistribution structure with a pad having a horizontal maximum length that varies between its upper and lower portions, along with specific insulating and conductive patterns, to enhance electrical connectivity and reliability, including the use of bumps and insulating layers to improve contact areas and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a general PCB is used to connect the semiconductor chip to external components, then the connection is simple and easy to manufacture, but the semiconductor chip size cannot be reduced further
Solution Approach 1:
The pad structure implements nesting by placing the upper pad portion within the opening of the lower pad portion, creating a nested configuration where the upper pad (with larger horizontal maximum length) is positioned inside the opening of the lower pad (with smaller horizontal maximum length). This nested arrangement allows the redistribution structure to achieve compact connectivity while enabling chip size reduction, resolving the contradiction between miniaturization and structural complexity.
Solution Approach 2:
The invention transitions from a two-dimensional planar connection (general PCB) to a three-dimensional stacked structure with multiple pad portions at different vertical levels. The upper and lower pad portions are arranged at different heights with the upper pad positioned within the opening of the lower pad, creating vertical stacking that enables space-efficient connectivity and supports further chip size reduction while maintaining connection functionality.
2Reliability
If the pad structure is simplified for ease of manufacture, then manufacturing is easier, but the contact area and electrical connection reliability are reduced
Solution Approach 1:
The pad structure implements local quality by differentiating the dimensions and positions of the upper and lower pad portions. The upper pad portion has a larger horizontal maximum length and is positioned within the opening of the lower pad, creating localized variations in pad geometry. This local differentiation optimizes electrical contact area and connection reliability at critical interfaces while maintaining manufacturability through standardized fabrication processes.
Data Source
AI summary
A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.