Semiconductor Pad Reinforcement with Copper Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to signal propagation delays due to parasitic resistance and capacitance, and low-k insulating layers used to mitigate this are susceptible to damage from wire bonding, requiring reinforcement while maintaining optimal etching conditions.
Innovation Solution
A semiconductor device with a wire-bonding electrode pad, interconnections, and reinforcing elements, where the reinforcing elements are sized differently depending on their location, with larger elements beneath the pad and smaller ones among interconnections, all composed of copper, and an apparatus to design these patterns to optimize etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k insulating interlayer is used to suppress parasitic capacitance, then signal propagation speed is improved, but physical strength of the insulating layer deteriorates making it susceptible to damage from wire bonding
Solution Approach 1:
The patent combines low-k insulating material with copper reinforcing elements to create a composite structure. The low-k material (SiOC, SiC, SiOF, porous SiO2, or porous SiOC) suppresses parasitic capacitance while the copper reinforcing elements embedded within provide mechanical strength to withstand wire bonding impacts, resolving the contradiction between electrical performance and mechanical durability
Solution Approach 2:
The patent applies reinforcement selectively in the pad area where wire bonding occurs, rather than uniformly throughout the entire insulating layer. Large reinforcing elements are positioned specifically beneath wire-bonding electrode pads to provide localized mechanical support where needed, while maintaining the low-k properties in other areas for optimal signal propagation
2Strength
If large reinforcing elements are formed in pad area to protect low-k insulating layer, then physical strength is improved, but etching process conditions fluctuate
Solution Approach 1:
The patent implements spatially varying reinforcement strategies: large reinforcing elements are formed only in pad areas requiring mechanical protection, while smaller reinforcing elements are formed in interconnection areas. This localized differentiation maintains etching process stability by limiting large element formation to specific regions, reducing overall process fluctuation while providing necessary strength where required
Solution Approach 2:
The patent divides the reinforcing elements into two distinct sets based on location and function: large reinforcing elements in pad areas for mechanical protection, and smaller reinforcing elements in interconnection areas for moderate support. This segmentation allows the etching process to be optimized for each region, reducing overall process variability while achieving localized strength requirements
3Volume of moving object
If miniaturization is advanced to reduce device size, then integration density is improved, but parasitic resistance and capacitance increase causing signal propagation delay
Solution Approach 1:
The patent changes the dielectric parameter of the insulating interlayer by using low-k materials (SiOC, SiC, SiOF, porous SiO2, or porous SiOC) with smaller dielectric constants than conventional silicon dioxide. This parameter change reduces parasitic capacitance in the miniaturized structure, compensating for the increased capacitance effects caused by scaling and maintaining signal propagation speed despite reduced device dimensions
Data Source
AI summary
In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.