Semiconductor Pad Layout for Creepage Discharge Suppression

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Solution Overview

Problem

Existing semiconductor devices face challenges in suppressing creeping discharges and deterioration of insulating layers due to the proximity of high and low potential conductive layers, leading to reliability issues.

Innovation Solution

A semiconductor device design featuring a semiconductor chip with a first conductive layer at a lower potential and a second conductive layer at a higher potential, separated by an insulating layer, with a pad configuration that increases the creepage distance between them, thereby reducing the occurrence of creeping discharges and protecting the insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the first pad is formed in a region opposing the second conductive layer to reduce device area, then the device area is reduced, but creeping discharges occur between the high and low potential conductive layers

Engineering Contradiction:
Improvedevice areaVSAvoidcreeping discharge resistance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The pad region is displaced from the vertical projection overlap (2D opposing relationship) to a lateral separation arrangement. By changing the spatial dimension of pad placement from directly opposing to laterally separated, the creepage distance is increased while maintaining compact device area, thus resolving the contradiction between area reduction and creeping discharge resistance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the first pad is positioned close to the second conductive layer to improve electrical connection, then the electrical connection is improved, but the insulating layer deteriorates due to creeping discharges

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidinsulating layer deterioration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The insulating layer is enhanced with a protective structure that acts as an intermediary barrier between the first pad (low potential) and the second conductive layer (high potential). This intermediary structure increases the creepage distance and prevents harmful creeping discharges from reaching the insulating layer, thereby protecting it from deterioration while maintaining reliable electrical connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the creepage distance between high and low potential conductive layers is increased to suppress creeping discharges, then the creeping discharge resistance is improved, but the device area increases

Engineering Contradiction:
Improvecreeping discharge resistanceVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing creepage distance in the vertical direction (which would increase device thickness and area), the design utilizes lateral separation in the horizontal plane. The first pad is positioned in a region separated in the first direction from the region opposing the second conductive layer, effectively increasing creepage distance through dimensional reconfiguration rather than simple expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20230387041A1Semiconductor device and semiconductor module
Publication Date: 2023.11.30 ROHM CO LTD
  • US20230387041A1 patent drawing
  • US20230387041A1 patent drawing
  • US20230387041A1 patent drawing

AI summary

A semiconductor device includes a semiconductor chip that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor chip and connected to a first potential, a second conductive layer that opposes the first conductive layer of the principal surface in a normal direction and is connected to a second potential higher than the first potential, an insulating layer that is formed between the first conductive layer and the second conductive layer, and a first pad that is formed in a region separated from a region that opposes the second conductive layer in a first direction in a plan view when the semiconductor chip is viewed in the normal direction and that is electrically connected to the first conductive layer.