Parallel Semiconductor Pad Layout for Uniform Current Sharing

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Solution Overview

Problem

In semiconductor devices with parallel-connected semiconductor elements, there is a difference in current paths leading to uneven current distribution, which can lead to increased load on one element and reduced lifespan of the other.

Innovation Solution

The semiconductor device aligns semiconductor elements along a specific direction, using a pad portion with a closed region defined by three vertices to evenly distribute current among elements, ensuring they are connected in parallel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If semiconductor elements are connected in parallel to achieve larger capacity and higher output, then the power handling capability is improved, but the current distribution becomes uneven due to differences in current path lengths

Engineering Contradiction:
Improvepower handling capabilityVSAvoidcurrent distribution uniformity
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies asymmetry by intentionally designing the pad portion with an uneven shape that compensates for the symmetric arrangement of semiconductor elements. The pad portion extends farther in directions corresponding to longer current paths, creating an asymmetric current distribution area that balances the total current path length from each semiconductor element to the terminal, thereby achieving uniform current distribution while maintaining parallel connection for high power capability

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the geometric parameters of the pad portion to control current distribution. By adjusting the extension length and shape of the pad portion in different directions, the patent optimizes the current path characteristics. This parameter adjustment ensures that despite different physical distances from semiconductor elements to terminals, the effective current path lengths become substantially equal, resolving the current distribution uniformity issue

Inventive Principle:
Principle #35Parameter changes

2Productivity

If semiconductor elements are arranged in parallel configuration, then the output capacity is increased, but the load distribution becomes uneven causing reduced lifespan

Engineering Contradiction:
Improveoutput capacityVSAvoidsemiconductor element lifespan
Core Design Contradiction:
ProductivityVSDuration of action of stationary object

Solution Approach 1:

The asymmetric pad portion design compensates for the symmetric semiconductor element arrangement. By making the pad portion extend unevenly in different directions, the patent creates balanced current paths that distribute load uniformly across all parallel-connected semiconductor elements, preventing any single element from bearing excessive load and thereby extending overall system lifespan while maintaining high output capacity

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent achieves equipotentiality in terms of current path characteristics by designing the pad portion such that the total current path length from each semiconductor element to the terminal is substantially equal. This equalizes the electrical conditions for current flow through each element, ensuring uniform load distribution and preventing premature failure of any individual element

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentUS20260090484A1Semiconductor device
Publication Date: 2026.03.26 ROHM CO LTD
  • US20260090484A1 patent drawing
  • US20260090484A1 patent drawing
  • US20260090484A1 patent drawing

AI summary

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.