Semiconductor Pad Structure for Uniform Dielectric Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of system-on-integrate-chip (SoIC) packages due to smaller geometry sizes and higher functional density leads to challenges in forming conductive pads with different profiles, resulting in loading effects that affect the reliability and yield of semiconductor structures, particularly during dielectric layer formation and planarization processes.
Innovation Solution
The method involves forming conductive pads with varying heights by using different etch stop layers and controlling polish end points, along with specific etching processes to alleviate loading effects, ensuring that dielectric layers are uniformly formed without over-etching, thereby improving the yield and reliability of SoIC packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conductive pads with different profiles are formed to achieve higher functional density, then the functional density increases, but loading effects occur during dielectric layer formation affecting reliability
Solution Approach 1:
The patent applies local quality by forming different etch stop layers at different locations corresponding to conductive pads of different heights. Each location receives a tailored etch stop layer thickness that matches the specific pad height requirements, allowing the dielectric layer to be uniformly deposited while accommodating local variations in pad profiles without causing loading effects
Solution Approach 2:
The patent implements preliminary action by forming etch stop layers before depositing the dielectric layer. This preliminary structuring ensures that when the dielectric layer is subsequently deposited, the loading effects are already mitigated, preventing reliability issues before they occur during the main fabrication process
2Length of moving object
If conductive pads with different profiles are formed to achieve smaller geometry sizes, then the geometry size decreases, but loading effects occur during planarization affecting manufacturing precision
Solution Approach 1:
The patent applies local quality by positioning specific etch stop layers at locations corresponding to conductive pads of different heights. This localized approach ensures that each pad region receives the appropriate etch stop protection, enabling uniform dielectric layer formation and accurate planarization despite variations in pad profiles, thereby maintaining manufacturing precision at smaller geometries
Solution Approach 2:
The patent implements preliminary action by pre-forming the etch stop layer structure before dielectric layer deposition and planarization. This advance preparation ensures that the loading effects are mitigated before the critical planarization step, allowing for precise control of the final surface topology even when working with smaller geometry sizes
3Ease of manufacture
If conventional methods are used to form conductive pads, then the process is simpler, but over-etching occurs affecting yield
Solution Approach 1:
The patent implements preliminary action by forming etch stop layers before the dielectric layer deposition and bonding structure formation processes. This preliminary protective layer prevents over-etching of conductive pads during subsequent etching steps, ensuring that pads are not damaged while still allowing the etching process to proceed effectively, thus maintaining high yield without significantly complicating the overall manufacturing process
Solution Approach 2:
The patent uses etch stop layers as intermediary protective structures between the conductive pads and the etching process. These intermediary layers act as sacrificial barriers that protect the conductive pads from over-etching while allowing the dielectric and bonding structures to be properly formed, thereby preventing yield loss without requiring fundamental changes to the manufacturing approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of semiconductor structures by ensuring satisfactory electrical connections and preventing over-etching of conductive pads, thereby improving the yield and reliability of SoIC packages by addressing the loading effect issues.
Implementation Method 1
performing a chemical mechanical polishing (CMP) process
Implementation Method 2
performing an etching process to form openings in the dielectric structure
Data Source
AI summary
A method includes providing a workpiece having a first conductive pad and a second conductive pad over a substrate, a topmost point of the second conductive pad is above that of the first conductive pad by a height difference, conformally forming a first etch stop layer on the first and the second conductive pads, forming a dielectric structure over the first etch stop layer, performing a planarization process to the dielectric structure, and after the performing of the planarization process, conformally depositing a dielectric layer over the workpiece, the dielectric layer including a first portion disposed directly over the first conductive pad and a second portion disposed directly over the second conductive pad, where a thickness difference between a thickness of the first portion of the dielectric layer and a thickness of the second portion of the dielectric layer is less than the height difference.