Semiconductor Pad Stack With Dual Etch Stops Against Delamination
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Solution Overview
Problem
The coefficient of thermal expansion mismatch between different materials in semiconductor devices leads to stress and delamination during manufacturing and use, particularly affecting etch stop layers, which can damage underlying layers during wet etching.
Innovation Solution
The use of multiple etch stop layers with different materials, such as tantalum oxide and tantalum, silicon nitride, to protect underlying layers from etching damage by halting the etching process and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple etch stop layers with different materials are used, then protection against delamination and etching damage is improved, but device complexity increases
Solution Approach 1:
The patent divides the protective function into multiple separate etch stop layers (first etch stop layer and second etch stop layer) with different materials. Each layer is positioned at different depths and provides protection against specific etching threats, thereby segmenting the overall protection mechanism to achieve comprehensive reliability without requiring a single complex material solution.
Solution Approach 2:
The patent employs composite material strategy by combining different etch stop layer materials (such as silicon nitride, silicon oxide, or other dielectric materials) with complementary etching resistance properties. This composite approach allows each material to resist specific etchants, providing multi-layered protection that addresses the complexity-reliability contradiction through material diversity rather than structural oversimplification.
2Reliability
If etch stop layers are formed to prevent delamination, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by positioning etch stop layers at specific locations within the semiconductor structure where delamination risk is highest. The first etch stop layer is formed between the first conductive layer and the substrate, while the second etch stop layer is formed between the second conductive layer and the first conductive layer. This localized placement strategy ensures manufacturing precision is focused only where critical, rather than requiring uniform high precision throughout the entire device.
Solution Approach 2:
The etch stop layers are formed in advance during the manufacturing process, before the actual etching operations that could cause delamination. By pre-positioning these protective layers with appropriate materials and thicknesses, the patent reduces the precision requirements during subsequent etching steps, as the etch stop layers themselves provide the necessary boundaries and protection.
Data Source
AI summary
A semiconductor device includes two etch stop layers to prevent delamination and damage to underlying components. Two passivation layers are disposed on a substrate, with a metal pad exposed through the passivation layers and contacting a top metal component of the substrate. The first etch stop layer is formed on the second passivation layer and the metal pad. A third passivation layer is formed on the substrate with an opening to the metal pad, which is covered by the first etch stop layer. The second etch stop layer is formed on the third passivation layer and in the opening on the second etch stop layer. A bottom metal film/conductive component is formed on the second etch stop layer, photoresist is applied, and wet etching is performed. The metal pad is protected from damage caused by delamination of the second etch stop layer from the first etch stop layer.