Semiconductor Pad Electrode Oxidation Control
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Solution Overview
Problem
In the wafer process package, high-temperature heat processing during the assembly of non-volatile memory can lead to data loss, and the accuracy of memory testing is compromised due to the hard Ni layer on the Cu wiring, causing increased contact resistance and defective solder bonding.
Innovation Solution
The method involves forming a semiconductor device with a semiconductor substrate having first and second pad electrodes, with metal films on their surfaces, and forming insulating films with specific openings to expose these metals, while applying an organic reaction layer to prevent oxidation and allowing for reliable testing and solder bump formation without Au plating, which reduces costs and improves bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Au plating is performed on the pad of the rearrangement wiring to reduce contact resistance, then the contact resistance with the probe decreases, but Ni oxidizes on the Au-plated film during retention baking, leading to increased contact resistance and defective solder bonding
Solution Approach 1:
The patent extracts the Au plating step from the manufacturing process. Instead of applying Au plating to reduce contact resistance, the invention uses the Ni layer directly by controlling oxidation through organic reaction layer formation and selective removal, thereby eliminating the source of Ni oxidation that compromises solder bonding reliability
Solution Approach 2:
The patent employs a cost-effective approach by eliminating expensive Au plating material. The Ni layer is used directly with controlled oxidation management through organic reaction layers, providing a cheaper alternative that achieves both low contact resistance and reliable solder bonding without the reliability issues caused by Au plating
2Loss of information
If memory testing is performed before forming rearrangement wiring, then data loss can be detected, but the test accuracy decreases due to large contact resistance caused by the hard Ni layer on Cu wiring
Solution Approach 1:
The patent applies preliminary action by forming the organic reaction layer on the Ni layer before memory testing. This pre-treatment reduces contact resistance at the probe contact point, enabling accurate memory testing to be performed before rearrangement wiring formation without compromising test accuracy due to high contact resistance
Solution Approach 2:
The patent changes the physical-chemical parameters of the Ni layer surface by forming an organic reaction layer. This modification reduces the hardness and contact resistance of the Ni layer, allowing accurate memory testing to proceed before rearrangement wiring formation while still enabling subsequent solder bonding after organic layer removal
3Reliability
If retention baking is performed at 250°C for 72 hours to test non-volatile memory, then data retention can be verified, but any subsequent high-temperature processing causes data loss
Solution Approach 1:
The patent segments the manufacturing process into distinct phases: memory programming, retention baking for data retention verification, and subsequent rearrangement wiring formation. By separating these processes and using organic reaction layers to protect the Ni layer during high-temperature wiring formation, the invention enables data retention testing while preventing data loss in subsequent processing
Solution Approach 2:
The patent applies beforehand cushioning by forming organic reaction layers on the Ni layer before subsequent high-temperature processing steps. These organic layers act as protective cushions that prevent direct oxidation of the Ni layer during rearrangement wiring formation, thereby preventing data loss while allowing necessary high-temperature processing to proceed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the memory test by preventing data loss during high-temperature processing and ensuring accurate solder bonding, while reducing costs by eliminating the need for Au plating and maintaining the integrity of the Ni layer.
Implementation Method 1
leaving an organic reaction layer on each surface of the first pad electrode and the wiring
Implementation Method 2
after forming the fourth opening, heat processing is performed on the semiconductor substrate
Data Source
AI summary
To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.