Semiconductor Pad Electrode Void Prevention
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Solution Overview
Problem
In semiconductor devices using high frequency waves, reducing the capacity of the pad electrode while maintaining adherence intensity between the pad electrode and the connecting terminal is challenging, as conventional designs often result in void formation leading to increased electrical resistance and reduced adherence intensity due to the small contact area and voids formed during the printing process.
Innovation Solution
The configuration includes a lower pad layer, an insulating layer positioned away from the surrounding area to form a recess, and an upper pad layer that covers the lower pad layer and extends to the upper face of the insulating layer, increasing the contact area and preventing void formation by ensuring the upper pad layer covers the entire recess area, thereby enhancing adherence intensity between the pad electrode and the connecting terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pad electrode is made small to reduce capacity, then the capacity is reduced, but the contact area between the upper pad layer and connecting terminal is reduced leading to reduced adherence intensity
Solution Approach 1:
The upper pad layer is extended in the planar dimension to have an area larger than the lower pad layer, compensating for the small contact area issue while maintaining reduced pad electrode capacity. This dimensional extension provides sufficient adhesion area for the connecting terminal without increasing the vertical profile or capacity-critical dimensions.
2Device complexity
If the insulating layer covers the surrounding of the lower pad layer, then the structure is compact, but voids are formed in the recess when connecting terminal is formed leading to increased electrical resistance
Solution Approach 1:
The insulating layer is extracted or removed from the region directly surrounding the lower pad layer, creating a recess space. This extraction prevents void formation during connecting terminal formation while maintaining structure compactness through strategic material removal rather than addition.
Solution Approach 2:
The recess space is preliminarily formed by positioning the insulating layer away from the lower pad layer surrounding before the connecting terminal is formed. This preliminary structural preparation ensures that no voids will form during subsequent terminal formation processes, preventing electrical resistance issues before they occur.
3Quantity of substance
If the upper pad layer has the same area as the lower pad layer, then the capacity is reduced, but the adherence intensity is insufficient when connecting terminal is provided
Solution Approach 1:
The upper pad layer is designed with different local qualities - it has a larger area than the lower pad layer specifically in the region where the connecting terminal will be formed. This local area expansion provides sufficient adhesion surface for the terminal while keeping the overall pad electrode capacity reduced through controlled dimensional differences.
Data Source
AI summary
A semiconductor device includes a lower pad layer, an insulating layer and an upper pad layer. The lower pad layer is provided on a semiconductor substrate. The insulating layer is away from a surrounding of the lower pad layer so that a space having a recess on a surface between the lower pad layer and the insulating layer is formed. The upper pad layer covers over the lower pad layer and the space, extends to an upper face of the insulating layer, and has an area larger than that of the lower pad layer.