3D Semiconductor Pad Structure Etching via Segmented Regions

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Solution Overview

Problem

In 3D semiconductor devices, the increase in the number of layers in a multi-layer pad structure leads to a significant increase in the thickness of the etch stop layer, reducing the process window and making it difficult to effectively connect contacts to pads due to the varying aspect ratios of contacts.

Innovation Solution

A manufacturing method involving a multi-layer structure with alternately stacked conductive and dielectric layers, where the heights of conductive layers in different regions are varied, allowing for separate etching processes using different filling layers to form openings without the need for an etch stop layer, thereby maintaining a stable process window.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of layers of the multi-layer pad structure is increased, then the integration density and performance of the semiconductor device are improved, but the thickness of the etch stop layer must be significantly increased, which reduces the process window and makes it difficult to effectively form contacts

Engineering Contradiction:
Improveintegration densityVSAvoidprocess window
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the multi-layer pad structure into two distinct regions: a first region with a smaller number of stacked layers and a second region with a larger number of stacked layers. This segmentation allows each region to be etched independently with optimized etch stop layer thickness, resolving the contradiction between integration density and process window. The first region can use a thinner etch stop layer for easier contact formation, while the second region uses a thicker etch stop layer to accommodate the increased number of layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different etch stop layer thicknesses to different regions of the substrate. The first region has a first etch stop layer thickness optimized for its smaller layer count, while the second region has a second etch stop layer thickness optimized for its larger layer count. This local differentiation allows each region to maintain an appropriate process window while achieving high overall integration density.

Inventive Principle:
Principle #3Local quality

2Reliability

If the thickness of the etch stop layer is increased to accommodate more layers, then the etching process can properly stop on the etch stop layer, but the space for contacts is reduced and the process window is reduced

Engineering Contradiction:
Improveetching process controlVSAvoidcontact space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The substrate is segmented into multiple regions, each with its own etch stop layer thickness optimized for the local layer count. This allows the etching process to have reliable stop control in each region without requiring a uniformly thick etch stop layer across the entire substrate, thereby preserving contact space in regions with fewer layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions are assigned different etch stop layer thicknesses based on their specific requirements. Regions with more layers receive thicker etch stop layers for reliable etching control, while regions with fewer layers receive thinner etch stop layers to maximize contact space. This local optimization resolves the contradiction between etching reliability and contact area.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9406609B1Opening structure and manufacturing method thereof and interconnection structure
Publication Date: 2016.08.02 MACRONIX INTERNATIONAL CO LTD
  • US9406609B1 patent drawing
  • US9406609B1 patent drawing
  • US9406609B1 patent drawing

AI summary

In a manufacturing method of an opening structure, a multi-layer structure including alternately stacked conductive layers and first dielectric layers is formed on a substrate. The conductive layers in a first region are lower than those in a second region. A second dielectric layer covering the multi-layer structure is formed. A patterned mask layer is formed on the second dielectric layer. A first filling layer covering the second dielectric layer exposed by the patterned mask layer is formed in the second region. First openings exposing the conductive layers in the first region are formed by using the first filling layer and the patterned mask layer as a mask. The first filling layer is removed. A second filling layer filling the first openings is formed. Second openings exposing the conductive layers in the second region are formed by using the second filling layer and the patterned mask layer as a mask.