Semiconductor Pad Layout With Inter-Pad Gate Runner Routing
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in utilizing the space between pads on a semiconductor substrate, where the region between pads is not effectively utilized for transistor and diode portions, leading to suboptimal device performance.
Innovation Solution
The semiconductor device incorporates a gate runner portion that transfers gate voltage to the transistor portion, with a configuration of first and second gate runners and dummy trench portions, allowing the transistor portion to be disposed in inter-pad regions and enhancing the use of space between pads, while maintaining efficient voltage transfer and reducing voltage delay and attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pads are arrayed along the sides of the semiconductor substrate, then the device structure is simplified and manufacturing is easier, but the inter-pad regions are wasted and not effectively utilized
Solution Approach 1:
The semiconductor substrate is divided into multiple inter-pad regions between adjacent pads, and transistor portions are independently disposed in these segmented regions. This segmentation allows effective utilization of previously wasted spaces while maintaining the simple arrayed pad structure for ease of manufacture.
Solution Approach 2:
The invention utilizes the two-dimensional space between pads by disposing transistor portions in the inter-pad regions, effectively converting the wasted lateral space into functional areas. This dimensional utilization increases the active area without changing the pad arrangement pattern.
2Area of stationary object
If transistor portions are disposed in inter-pad regions, then the active area is increased, but gate voltage transfer distance and complexity increase
Solution Approach 1:
Gate runner portions are introduced as intermediary conductive structures that efficiently transfer gate voltages from gate electrodes to transistor portions disposed in inter-pad regions. These gate runners act as mediators that simplify the voltage transfer path and reduce complexity compared to direct connections.
Solution Approach 2:
Multiple gate runner portions are merged and extended to form a unified gate voltage distribution network that serves multiple transistor portions simultaneously. This merging approach reduces the overall complexity by sharing common voltage transfer paths rather than creating separate connections for each transistor.
3Ease of operation
If gate runners are extended to reach transistor portions in inter-pad regions, then voltage transfer is achieved, but voltage delay and attenuation increase
Solution Approach 1:
Gate runner portions are preliminarily extended and positioned to reach transistor portions in inter-pad regions during the device fabrication process. This preliminary action ensures optimal voltage transfer paths are established before final device operation, minimizing subsequent voltage delay and attenuation.
Solution Approach 2:
The gate runner portions are specifically designed with local quality optimizations in the inter-pad regions, including appropriate width, material selection, and routing patterns that minimize resistance and capacitance. This local optimization reduces voltage delay and attenuation while maintaining effective voltage transfer to distant transistor portions.
Data Source
AI summary
A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.