Semiconductor Pad Group Selective Transfer Unit for Testing
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Solution Overview
Problem
Existing semiconductor systems face challenges in effectively testing and correcting the interface characteristics of semiconductor devices with micro bump pads, particularly in ensuring proper data transmission and synchronization between components.
Innovation Solution
A semiconductor system comprising a first semiconductor device with a pad group, a second semiconductor device with a selective transfer unit and interface unit that couples pad groups to facilitate signal input/output and detect phase information signals, enabling synchronization and correction of data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CoC packaging technology is used to achieve high integration and high speed operation, then data transmission speed is improved, but testing and correction of interface characteristics becomes difficult
Solution Approach 1:
The patent introduces a test mode enable signal as an intermediary mechanism that activates a selective transfer unit. This unit can reroute signals through alternative paths (such as using bump pads instead of micro bump pads) during testing, while maintaining the original high-speed micro bump pad connections during normal operation. This resolves the contradiction by providing a mediating testing pathway without compromising the high-speed data transmission capability.
Solution Approach 2:
The patent implements dynamic signal routing capability where the connection path can be switched between micro bump pads (for high-speed operation) and bump pads (for testing). The selective transfer unit responds to the test mode enable signal to dynamically change the signal transmission path, allowing the system to adapt between high-speed mode and testing mode, thus resolving the contradiction between speed and testability.
2Speed
If micro bump pads with small diameter are used, then resistance and inductance are reduced improving transmission speed, but ease of testing and measurement is reduced
Solution Approach 1:
The patent segments the connection interface into two distinct types: micro bump pads for high-speed data transmission and larger bump pads for testing purposes. The selective transfer unit enables independent selection of these segments based on operational mode. This segmentation allows each type of pad to be optimized for its specific function without compromise.
Solution Approach 2:
The selective transfer unit acts as an intermediary that can redirect test signals to use the larger bump pads instead of the smaller micro bump pads. During normal operation, signals flow directly through micro bump pads for high speed. During testing, the intermediary reroutes signals through the easier-to-measure bump pads, resolving the contradiction between transmission speed optimization and testing ease.
3Productivity
If high integration of memory and controller is achieved through CoC packaging, then operation frequency is increased, but ability to perform data input/output testing is reduced
Solution Approach 1:
The patent implements multi-functionality by designing the second semiconductor device with both micro bump pads (for high-speed data I/O) and larger bump pads (for testing), along with a selective transfer unit. This universal interface can adapt to different operational requirements: high-speed operation mode or testing mode, thus resolving the contradiction between productivity and adaptability for testing.
Solution Approach 2:
The system dynamically switches between operational modes through the test mode enable signal. During normal high-frequency operation, the system uses micro bump pads for optimal performance. During testing operations, the system dynamically reconfigures to use bump pads through the selective transfer unit, maintaining both high productivity during operation and testing capability when needed.
Data Source
AI summary
A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal.