Stacked Semiconductor Package Pad Structure for Heat Dissipation

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Solution Overview

Problem

Existing semiconductor packages face challenges in efficiently releasing heat generated inside the package, leading to performance degradation due to thermal issues.

Innovation Solution

The semiconductor package incorporates a lower structure with a heat sink structure at the same height level as the pad structure, and a connection pattern that electrically and physically connects the lower and upper structures, enhancing heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple chips are incorporated in a single package, then package capacity is improved, but heat release capability deteriorates

Engineering Contradiction:
Improvepackage capacityVSAvoidheat release capability
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent transitions from planar chip arrangement to three-dimensional stacked configuration, placing an upper chip package above a lower chip package vertically. This spatial reorganization increases package capacity while maintaining heat release paths through the vertical dimension, with heat sinks extending laterally to dissipate heat from both upper and lower chips.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the heat dissipation function into separate components: upper chip package with its own heat sink, lower chip package with its own heat sink, and intermediate heat dissipation structures. This segmentation allows independent optimization of heat release paths for each chip, preventing thermal interference while maintaining high package capacity.

Inventive Principle:
Principle #1Segmentation

2Temperature

If heat sink structure is added to improve heat release, then temperature control is improved, but device complexity increases

Engineering Contradiction:
Improveheat release capabilityVSAvoidstructure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into integrated structures: the connection pattern between upper and lower chip packages serves both electrical interconnection and mechanical support functions; the intermediate layer between chips provides both structural spacing and heat dissipation pathways; heat sinks are integrated directly with the chip mounting substrates rather than being separate components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent designs multi-functional elements where the same structure performs multiple roles: the substrate serves as both mechanical support and electrical connection carrier; the connection pattern provides both electrical signaling and thermal conduction paths; the intermediate layer provides structural separation and heat dissipation simultaneously, reducing the need for dedicated heat release components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves heat sink characteristics, effectively releasing heat generated in the semiconductor package and preventing performance degradation.

Implementation Method 1

a heat sink structure... At least a portion of the heat sink structure may be at a same height level as at least a portion of the pad structure

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

improves heat sink characteristics, effectively releasing heat generated in the semiconductor package

Methodology Applied
Scientific EffectConvection: Convection

Data Source

PatentEP3667719B1Semiconductor packages
Publication Date: 2025.05.21 SAMSUNG ELECTRONICS CO LTD
  • EP3667719B1 patent drawingFigure 1
  • EP3667719B1 patent drawingFigure 2
  • EP3667719B1 patent drawingFigure 3

AI summary

Disclosed is a semiconductor package which includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.