Semiconductor Pad Interconnect Narrow Spacing Stress Dispersion
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Solution Overview
Problem
Existing semiconductor device structures fail to adequately reduce stress-induced cracks in insulating films and current leakage when interconnects are arranged below the pad, limiting chip size reduction and increasing costs.
Innovation Solution
A semiconductor device with a narrow spacing region between interconnects below the pad, where the spacing between adjacent interconnects is shorter than outside regions, and optionally including dummy interconnects and a tapered shape, to effectively disperse stress and reduce crack occurrence during electrical testing and assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interconnects are arranged below the pad to reduce chip size, then chip area is reduced, but stress concentration causes cracks in the insulating film
Solution Approach 1:
The patent applies local quality by creating a narrow spacing region with different interconnect spacing characteristics specifically below the pad area. The interconnect spacing is made narrower (e.g., 0.5-2.0 times the interconnect width) in this specific region compared to other areas, providing localized stress dispersion exactly where needed during probe testing and wire bonding operations.
Solution Approach 2:
The patent changes the spacing parameter between interconnects in the narrow spacing region below the pad. By reducing the spacing between adjacent interconnects in this specific region, the structural strength is enhanced and stress is better dispersed when external forces are applied during electrical testing or assembly processes.
2Strength
If interconnect spacing is reduced below the pad to strengthen structure, then stress dispersion is improved, but manufacturing precision requirements increase
Solution Approach 1:
The narrow spacing region is localized specifically below the pad area, limiting the area where tight spacing control is required. This regional approach concentrates manufacturing precision requirements to a specific zone rather than the entire chip, making the precision control more manageable and focused.
Solution Approach 2:
The patent applies the narrow spacing configuration partially, only in the region below the pad where stress occurs during testing and assembly. Other regions of the chip can maintain larger interconnect spacing, reducing overall manufacturing complexity while still providing the necessary structural reinforcement where needed.
3Area of stationary object
If elements are arranged below the pad to reduce chip size, then chip area is reduced, but stress causes current leakage and property variation
Solution Approach 1:
The narrow spacing region is specifically positioned below the pad where stress from probe testing and wire bonding occurs. This localized structural reinforcement protects the insulating film and underlying elements in the critical stress zone, preventing current leakage paths while allowing elements to be safely arranged below the pad area.
Solution Approach 2:
The enhanced interconnect structure with narrow spacing is prepared in advance below the pad area, creating a reinforced zone that cushions and absorbs stress before it can propagate to the insulating film and cause cracks or current leakage. This preventive structure is in place before testing or assembly operations occur.
Data Source
AI summary
A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad.