Semiconductor Pad Interconnection via Substrate Traces
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Solution Overview
Problem
Existing techniques for increasing packaging density and performance of semiconductor chips result in a larger interconnection substrate and higher pin count, making it difficult to stabilize power supply and maintain design flexibility.
Innovation Solution
Interconnecting nonadjacent pads on a semiconductor chip using traces on an interconnection substrate instead of internal conductors, allowing for a reduced number of external connection terminals and improved design flexibility while maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power-supply pads are provided to stabilize power supply, then power supply stability is improved, but the pin count increases
Solution Approach 1:
Multiple power-supply pads are electrically connected through conductive traces on the interconnection substrate, merging them into a single external terminal. This allows multiple pads to work together for stable power supply while presenting only one connection point externally, thus maintaining reliability without increasing pin count.
Solution Approach 2:
The interconnection substrate acts as an intermediary between the semiconductor chip and the external terminal. It provides conductive traces that electrically connect multiple power-supply pads to a single external terminal, enabling power stability through multiple pads while keeping the external interface simple.
2Quantity of substance
If the number of external connection terminals is increased to accommodate high pin count, then packaging density is improved, but device complexity increases
Solution Approach 1:
Multiple pads on the semiconductor chip are merged into fewer external terminals through the interconnection substrate. This reduces the number of external connections required while maintaining high packaging density on the chip side, thereby reducing device complexity.
Solution Approach 2:
The interconnection substrate segments the connection function by providing separate conductive traces for different signal types (power, ground, data) while consolidating them into fewer external terminals. This segmentation allows complex internal connections to be managed independently without increasing external complexity.
3Reliability
If internal conductors of a chip are used to interconnect pads, then interconnection is achieved, but resistance is high
Solution Approach 1:
The interconnection substrate serves as an intermediary that provides low-resistance conductive traces between pads. These traces have lower resistance compared to internal chip conductors, reducing energy loss while maintaining effective interconnection capability.
Solution Approach 2:
The patent replaces the mechanical/internal conductor structure within the chip with an external conductive trace structure on the interconnection substrate. This substitution allows for optimized trace geometry and material selection that achieves lower resistance compared to constrained internal chip conductors.
Data Source
AI summary
An object of the present invention is to solve the problem that the number of pads increases due to high packaging density and the size of semiconductor devices increases due to increase of the pad density. A semiconductor device according to the present invention uses a conductor trace on an interconnection substrate to interconnect two nonadjacent pads.