Semiconductor Pad Interconnects for CMP Dishing Prevention
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Solution Overview
Problem
The existing semiconductor device technologies face challenges in forming pad structures without dishing or poor filling during the chemical mechanical polishing (CMP) process, which affects the integrity and efficiency of interconnect formation.
Innovation Solution
The semiconductor device incorporates a pad structure with a plurality of pad interconnects, where the width of the interconnects is smaller than their height, and interconnect links are provided to connect adjacent interconnects, allowing for stable formation and preventing excessive etching and poor filling by optimizing the dimensions and layout of the pad interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bonding pad size is increased to about 100 μm×100 μm to meet electrical connection requirements, then sufficient electrical connection area is provided, but excessive chemical etching occurs at the center causing dishing
Solution Approach 1:
The large bonding pad area is segmented into multiple parallel strip-shaped interconnects. This allows the overall pad to maintain a large footprint (100 μm×100 μm) for sufficient electrical connection reliability, while each individual strip has a small width that prevents excessive chemical etching during CMP, thus avoiding dishing
Solution Approach 2:
The pad structure transitions from a two-dimensional continuous surface to a series of one-dimensional strips arranged in parallel. This dimensional change allows the pad to maintain large area for electrical connection while reducing the width dimension of each individual interconnect, thereby preventing excessive etching
2Manufacturing precision
If a lattice-shaped bonding pad structure is used to prevent dishing, then excessive etching is prevented, but the structure complexity increases and filling becomes more difficult
Solution Approach 1:
The bonding pad is segmented into simple parallel strip-shaped interconnects with uniform width and spacing, rather than using a complex lattice pattern. This segmentation achieves the goal of preventing dishing through reduced etching while maintaining structural simplicity that is easier to manufacture and fill compared to lattice structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents dishing and ensures stable, efficient formation of pad structures in a short time, reducing the risk of poor filling and variations in potential among interconnects, while also improving processing stability and electrical connectivity.
Implementation Method 1
the metal film 21′ is etched, not only mechanically, but also chemically. Therefore, when the bonding pad 21 having a size of about 100 μm×100 μm is to be formed by leaving the portion of the metal film 21′ in the groove 19b unremoved, the center of the portion of the metal film 21′ in the groove 19b tends to be etched excessively by chemical etching mainly, causing dishing.
Implementation Method 2
A chemical mechanical polishing (CMP) technique is used for formation of the bonding pad 21 in the damascene process.
Data Source
AI summary
A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.