Semiconductor Pad Layout for Wafer-Level Interface Resistance Testing
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Solution Overview
Problem
The challenge in semiconductor device technology is to ensure reliable and stable external terminals that connect semiconductor devices to external power sources or other devices, as they become smaller and more complex, requiring improved electrical connections and interface resistance testing.
Innovation Solution
A semiconductor device design featuring a substrate with multiple wiring layers, passivation layers, and trenches to expose test and bump pads, allowing for electrical connections between bump pads and test pads, enabling effective interface resistance testing before the sawing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor device is reduced in size to become lighter, thinner, and smaller, then the external terminal size is reduced, but the reliability of the external terminal deteriorates
Solution Approach 1:
The patent divides the external terminal structure into multiple segments including bump pads, test pads, wiring layers, and passivation layers. This segmentation allows for independent optimization of each component while maintaining overall reliability despite reduced device size.
Solution Approach 2:
The patent introduces multiple wiring layers stacked in the vertical dimension to compensate for the reduced horizontal size of external terminals. This multi-layer wiring structure maintains electrical connection reliability by providing redundant pathways and increased connection area in the vertical direction.
2Measurement precision
If multiple wiring layers and trenches are added to enable interface resistance testing, then the testing capability is improved, but the device complexity increases
Solution Approach 1:
The patent designs the multi-layer wiring structure and trenches to serve multiple functions: they provide electrical connections between bumps and simultaneously enable interface resistance testing. The test pads and wiring layers are configured to allow measurement of interface resistance without requiring additional external testing equipment or complex test structures.
Solution Approach 2:
The patent incorporates test pads and wiring configurations during the manufacturing process, before the device is completed. This preliminary setup of testing infrastructure allows for interface resistance measurements to be performed at the wafer level or during assembly, eliminating the need for complex post-manufacturing testing equipment.
Data Source
AI summary
A semiconductor device includes a substrate with first and second surfaces, a first test pad on the first surface of the substrate, a first bump pad on the first surface of the substrate and spaced apart from the first test pad in a first direction, a second bump pad on the first surface of the substrate and spaced apart from the first bump pad, a second test pad on the first surface of the substrate and spaced apart from the second bump pad in the first direction, a first wiring layer in the first direction and electrically connecting the first test pad to the first bump pad, a second wiring layer in the first direction, spaced apart from the first wiring layer, and electrically connecting the second test pad to the second bump pad, and a first bump connected to each of the first and second bump pads.