Semiconductor Pad Pattern with Landing Sidewall for High Integration
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve high integration density while overcoming limitations in pattern fineness due to expensive equipment and complex fabrication processes, which affect the cost and efficiency of semiconductor devices.
Innovation Solution
The semiconductor device features conductive patterns stacked on a substrate with specific pad patterns and sidewall structures, including a flat portion and a landing sidewall portion, optimized for high integration density, along with a method of fabricating these structures using alternating material layers and planarization processes to enhance pattern formation and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to achieve high integration density, then manufacturing precision may be improved, but device complexity and cost increase due to expensive equipment and complex processes
Solution Approach 1:
The patent transitions from two-dimensional planar patterns to three-dimensional vertical structures by forming pad patterns with landing sidewall portions that extend upward from flat portions. This dimensional change allows patterns to be stacked vertically, achieving higher integration density without requiring finer lateral patterning, thus reducing dependence on expensive high-resolution lithography equipment.
Solution Approach 2:
The pad pattern is segmented into distinct portions: a flat portion extending from the conductive pattern and a landing sidewall portion extending upward. This segmentation allows each portion to serve specific functions - the flat portion provides a broad base for alignment and connection, while the landing sidewall portion enables vertical stacking and compact integration, resolving the contradiction between precision and complexity.
2Ease of manufacture
If conventional pad patterns are used, then manufacturing simplicity may be maintained, but integration density decreases due to larger area occupation
Solution Approach 1:
The invention utilizes the vertical dimension by forming landing sidewall portions that extend upward from the flat portions of pad patterns. This allows multiple pad patterns to be stacked vertically, significantly reducing the horizontal area occupied by each unit memory cell while maintaining ease of manufacture through standard deposition and etching processes.
Solution Approach 2:
The pad patterns are arranged in a nested configuration where multiple pad patterns are positioned at different vertical levels, similar to nested dolls. This nesting approach maximizes space utilization in the vertical direction, achieving high integration density without complicating the manufacturing process.
Data Source
AI summary
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.