Semiconductor Device With Localized Pad Layer Thickness
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Solution Overview
Problem
In three-dimensional semiconductor devices with through-silicon vias (TSVs), the dielectric breakdown during manufacturing leads to malfunction due to high electric field intensity between the pad layers and the semiconductor substrate, causing leak currents and increased resistance, which is exacerbated by the long aspect ratio of contact plugs required for vertical stacking.
Innovation Solution
The semiconductor device design includes a first region with a larger distance from the insulating layer to the semiconductor substrate interface than the second region, reducing the electric field intensity and preventing dielectric breakdown by selectively etching the first region and using a protrusion on the pad layer as a protection element, thereby maintaining chip area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical stacking with long contact plugs is used to connect stacked semiconductor devices, then electrical connection is achieved, but dielectric breakdown occurs due to high electric field intensity
Solution Approach 1:
The pad layer is designed with different thicknesses in different regions: a first region with greater thickness near the through-silicon via contact plug to reduce electric field intensity and prevent dielectric breakdown, and a second region with smaller thickness for other functions. This local variation in pad layer quality resolves the contradiction by providing enhanced reliability where needed without compromising overall device performance.
2Reliability
If pad layer thickness is increased to prevent dielectric breakdown, then reliability improves, but chip area increases
Solution Approach 1:
Instead of uniformly increasing pad layer thickness across the entire chip, the invention applies thicker pad layer only in the first region where the through-silicon via contact plug is located and dielectric breakdown risk is highest. The second region maintains smaller thickness, thus preventing dielectric breakdown where critical while minimizing chip area expansion.
Solution Approach 2:
The pad layer is segmented into multiple regions with different thickness characteristics: a first region with greater thickness for electrical connection stability and a second region with smaller thickness. This segmentation allows the device to achieve reliability without proportionally increasing overall chip area.
Data Source
AI summary
A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second conductive layer, and a plurality of second conductors. The semiconductor layer has a first region and a second region. The first conductor is provided in the semiconductor layer. The first conductive layer is electrically connected to the first conductor. The first insulating layer is provided in the semiconductor layer with at least part of the first insulating layer being provided between the first conductive layer and the semiconductor layer. A distance from the first insulating layer to the first region is smaller than a distance to the second region. A first distance to the first region from a plane that includes a first interface between the first insulating layer and the first conductive layer is larger than a second distance from the plane to the second region.