Semiconductor Package Pad Layout for ESD and Power Integrity
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Solution Overview
Problem
Semiconductor devices face issues with power supply voltage integrity and Electrostatic Discharge (ESD) damage due to the increased inductance and resistance in redistribution patterns connecting center and edge pads, which can lead to deterioration of power supply voltage and potential damage from ESD.
Innovation Solution
Incorporating a semiconductor device design with a center ESD clamp circuit, control logic, and specific redistribution patterns connected via uppermost vias to reduce inductance and resistance, and implementing edge ESD clamp circuits adjacent to edge pads to protect against ESD, while maintaining efficient signal and power supply voltage transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If redistribution patterns are used to connect center pads to edge pads, then wire length is reduced, but power supply voltage integrity deteriorates due to increased inductance and resistance
Solution Approach 1:
The power supply path is segmented into multiple parallel redistribution patterns instead of using a single pattern. This divides the current path into several segments that carry current simultaneously, reducing the overall inductance and resistance while maintaining short wire length. The segmentation allows power to be distributed through multiple routes from edge pads to center pads.
Solution Approach 2:
Multiple redistribution patterns are merged/combined to form a parallel power distribution network. By combining multiple patterns that connect edge pads to center pads, the patent creates redundant current paths that reduce total inductance and resistance, thereby improving power supply voltage integrity while keeping the physical wire length short.
2Productivity
If edge pads are connected to redistribution patterns, then center pad structure efficiency is improved, but ESD damage risk increases around edge pads
Solution Approach 1:
ESD clamp circuits are preliminarily positioned and connected to edge pads before ESD events occur. These clamp circuits are pre-configured in the redistribution patterns adjacent to edge pads, ready to activate immediately when ESD strikes, clamping the voltage and diverting harmful current away from sensitive internal circuits.
Solution Approach 2:
ESD clamp circuits act as intermediary protection elements between edge pads and the internal semiconductor circuitry. When ESD occurs at edge pads, the clamp circuits intermediate the harmful effect by providing a controlled discharge path, preventing direct damage to the center pads and internal circuits while allowing the efficient center pad structure to function.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a peripheral circuit area including an input/output circuit, a electrostatic discharge (ESD) clamp circuit, and control logic, center pads above the peripheral circuit area in a vertical direction, orthogonal to an upper surface of the semiconductor substrate, and electrically connected to the input/output circuit and the center ESD clamp circuit, edge pads adjacent to a first edge of the semiconductor substrate and higher than the plurality of center pads in the vertical direction, and redistribution patterns connected to the plurality of edge pads and extending in a first direction, parallel to the upper surface of the semiconductor substrate. At least one redistribution pattern, among the redistribution patterns, is connected to at least one uppermost wiring pattern at the same height as the center pads by uppermost vias, on both sides of the center pads in the first direction.