Semiconductor Pad Layout Noise Risk Calculation
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Solution Overview
Problem
Current semiconductor integrated circuit design methods lack a systematic approach for properly laying out power supply pads to mitigate simultaneous switching noise, leading to prolonged design times and inefficiencies in chip layout and package design.
Innovation Solution
A semiconductor integrated circuit design supporting method and system that includes a memory unit for storing cell information and a drive factor definition file, a pad laying out section for tentatively laying out power supply and input-output pads, a package virtual designing section for creating package drawings, an electric characteristics data calculating section for calculating inductance, and a noise risk calculating section for assessing noise risk, allowing for initial examination of noise risk during the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If noise risk examination is performed after chip layout and package designing are completed, then the design process follows the conventional sequence, but the design time is prolonged due to required backtracking and rework when noise problems are detected
Solution Approach 1:
The patent performs noise risk examination at the pad layout stage, before chip layout and package designing are completed. The noise risk calculating section calculates noise risk for each pad based on the tentative pad layout, allowing designers to identify and correct noise issues early in the design process, thereby avoiding time-consuming backtracking and rework later
2Quantity of substance
If the number of power supply pads is estimated using the conventional method (multiplying drive factor by inductance coefficient and dividing by noise tolerance), then the pad quantity can be determined, but there is no established method for properly laying out these pads to mitigate simultaneous switching noise
Solution Approach 1:
The patent implements a feedback mechanism where the noise risk calculating section calculates noise risk for each pad based on the tentative pad layout, and this noise risk information is fed back to guide the optimization of pad layout. The pad layout is adjusted to reduce noise risk, creating an iterative design process that continues until noise requirements are met
3Productivity
If tentative pad layout is created without noise risk calculation, then the design process is simpler and faster, but the risk of simultaneous switching noise cannot be examined until later stages
Solution Approach 1:
The patent performs noise risk calculation at the pad layout stage, before chip layout and package designing are completed. The noise risk calculating section calculates noise risk for each pad based on the tentative pad layout, allowing designers to identify and correct noise issues early in the design process, thereby avoiding time-consuming backtracking and rework later
Data Source
AI summary
A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of each of the plurality of IO cells, a pad laying out section which tentatively lays out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, a package virtual designing section which prepares a package drawing based on coordinates of the power supply pads and the input-output pads, which have been tentatively laid out, an electric characteristics data calculating section which calculates inductance of the power supply pads, using the package drawing, and a noise risk calculating section which calculates noise risk of each of the input-output pads, using the inductance and the drive factor definition file.