Semiconductor Module Pad Layout for Lower Conduction Resistance
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Solution Overview
Problem
Semiconductor devices mounted on substrates face challenges in efficiently managing high current flows, leading to increased conduction resistance and heat generation, which complicates the design of current paths and affects charging times in devices like smartphones.
Innovation Solution
A semiconductor device with a chip-size package type configuration, featuring two vertical MOS transistors and a semiconductor substrate acting as a common drain region, is face-down mounted on a substrate with optimized source and gate pad arrangements. This configuration allows for reduced conduction resistance by aligning gate pads and overlapping current paths, thereby simplifying substrate wiring and enhancing current flow efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device layout is used, then device structure is simple, but conduction resistance increases and current flow efficiency decreases
Solution Approach 1:
The patent applies asymmetry by positioning the first and second gate pads at different locations on the semiconductor chip, with the first gate pad connected to the first source region and the second gate pad connected to the second source region. This asymmetric arrangement allows for optimized current paths that reduce conduction resistance while maintaining a relatively simple overall device structure. The gate pads are strategically placed to minimize resistance without requiring complex additional components.
2Reliability
If main current path is optimized for efficiency, then conduction resistance decreases, but device structure becomes more complex
Solution Approach 1:
The patent merges the current paths by having both the first and second source regions connect to the common source region, which then connects to the source electrode. This merging approach allows the main current to flow through a consolidated path with lower conduction resistance. The first and second MOS transistors share common elements (source region, source electrode, drain electrode, substrate), reducing the need for separate complex current paths while achieving efficient current flow.
Solution Approach 2:
The patent implements universality through the common source region and common source electrode that serve both the first and second MOS transistors. This multi-functional design allows a single current path structure to handle current from multiple transistor channels, reducing conduction resistance without requiring duplicate separate paths for each transistor, thereby simplifying the overall current path structure.
3Reliability
If gate pads are positioned for optimal current flow, then conduction resistance reduces, but substrate wiring complexity increases
Solution Approach 1:
The patent extracts the gate control functions to separate gate pads located on the chip surface, with the first gate pad connected to the first gate electrode and the second gate pad connected to the second gate electrode. This extraction allows the gate control signals to be applied independently while the main current flows through the optimized common source path. The substrate wiring is simplified because the gate pads are positioned to minimize interference with the main current paths, separating control signaling from power delivery routes.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.