Semiconductor Package Pad Layout for High-Speed Signal Integrity
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Solution Overview
Problem
Current semiconductor packages face challenges in maintaining high-speed signal integrity due to impedance discontinuities caused by varying substrate and terminal widths, leading to signal reflection and degradation.
Innovation Solution
The semiconductor package design incorporates substrate pads and connecting terminals of varying widths to reduce capacitance and impedance discontinuities, with narrower pads and terminals for high-speed signals, enhancing signal quality and reducing loss across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform width substrate pads and connecting terminals are used, then manufacturing is simpler, but impedance discontinuities cause signal reflection and degradation
Solution Approach 1:
The patent applies local quality by varying the width of substrate pads and connecting terminals according to their specific function and signal type. Different regions of the package have different pad widths optimized for their particular signal requirements, with narrower pads for high-speed signals and wider pads for power and ground signals, thereby reducing impedance discontinuities while maintaining manufacturing feasibility
2Reliability
If narrower substrate pads and connecting terminals are used for high-speed signals, then capacitance and impedance discontinuities are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the substrate pads and connecting terminals into different width categories based on signal type. By dividing the interconnection structure into distinct groups (narrow pads for high-speed signals, wide pads for power/ground), the design achieves optimized electrical performance while simplifying the manufacturing process through standardized width specifications for each segment
3Reliability
If varying widths of substrate pads and connecting terminals are implemented, then capacitance is reduced and impedance discontinuities are minimized, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the width parameter of substrate pads and connecting terminals based on signal frequency and type. This controlled variation of the width parameter reduces capacitance and impedance discontinuities for high-speed signals while maintaining appropriate dimensions for power and ground signals, thereby improving signal quality without excessive complexity
Data Source
AI summary
A semiconductor package includes a substrate having opposite first and second surfaces; (1-1)-th substrate pads and (1-2)-th substrate pads on the first surface of the substrate; first connecting terminals on the (1-1)-th substrate pads and the (1-2)-th substrate pads; (2-1)-th substrate pads and (2-2)-th substrate pads on the second surface of the substrate; an interposer on the second surface of the substrate; second connecting terminals between the (2-1)-th substrate pads, the (2-2)-th substrate pads, and the interposer; and a first semiconductor chip on the interposer. The (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads. The (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads. The (1-1)-th substrate pads and the (2-1)-th substrate pads transmit first signals, ground signals, or power signals. The (1-2)-th substrate pads and the (2-2)-th substrate pads transmit second signals that are faster than the first signals.