Semiconductor Pad Layout for High Aspect Ratio TCP Packaging
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Solution Overview
Problem
Semiconductor chips with high aspect ratios face lead-broken problems during tape carrier packaging due to the weak strength of leads, which are exacerbated by the small pad pitch and limited area for pad arrangement, making miniaturization challenging.
Innovation Solution
A pad layout structure where pads on the left and right sides have a greater longitudinal width, and pads on the upper and lower sides have a greater transverse width compared to those at the center, distributing the force more evenly and increasing the lead width to enhance strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pad pitch is minimized to arrange a large number of pads in a limited area, then the number of pads that can be arranged increases, but the lead width decreases and lead strength decreases causing lead-broken problems
Solution Approach 1:
The patent applies local quality by making pads at different locations have different dimensions. Specifically, pads arranged at both edges of the semiconductor chip are designed with larger dimensions than pads arranged at centers of sides. This local differentiation allows edge pads to provide stronger support for leads while center pads maintain minimal size, thereby resolving the contradiction between minimizing pad pitch and maintaining lead strength.
2Strength
If the longitudinal length of the semiconductor chip is increased to prevent lead-broken problems, then the lead strength increases, but the chip size increases and miniaturization becomes difficult
Solution Approach 1:
Instead of uniformly increasing the entire chip size, the patent applies local quality by selectively enlarging only the pads at the edges of the chip. This localized approach provides the necessary lead support strength exactly where it is needed (at the edges) without increasing the overall chip dimensions, thus resolving the contradiction between lead strength and chip miniaturization.
Solution Approach 2:
The patent resolves the contradiction by shifting from a one-dimensional solution (increasing chip length) to a two-dimensional solution (varying pad dimensions across the chip surface). By making edge pads larger in the lateral direction rather than extending the chip longitudinally, the patent achieves the necessary lead support while maintaining compact chip dimensions.
3Volume of moving object
If the lead width is decreased to achieve compact packaging, then the package size decreases, but the lead strength decreases causing lead-broken problems
Solution Approach 1:
The patent applies local quality by creating non-uniform pad dimensions where edge pads are larger and center pads are smaller. This allows the overall package to remain compact while providing localized reinforcement at edge locations where leads are most vulnerable, thus resolving the contradiction between compact packaging and lead strength.
Data Source
AI summary
Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.