Semiconductor Pad Layout for Wiring Uniformity
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Solution Overview
Problem
The existing semiconductor device configurations face challenges in achieving uniformity in wiring lengths for data signals, which hinders high-speed operation, especially in DDR DRAMs, due to constraints in pad arrangement and bond finger layout, leading to significant differences in propagation delay times and limited space for additional bond fingers.
Innovation Solution
The semiconductor device features a chip with pads for data signals arranged symmetrically on opposite sides and pads for command/address signals on a third side, with corresponding bond fingers on the substrate, allowing for extended wiring lengths and reduced propagation delay times, and includes additional bond fingers for power supply reinforcement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pads for data signals are arranged on all four sides of the chip, then wiring length uniformity is improved, but chip area increases
Solution Approach 1:
The patent transitions from arranging pads only on peripheral sides to including corner regions in the pad arrangement. This dimensional expansion allows data signal pads to be positioned at corners, enabling more flexible wiring path design that achieves uniform wiring lengths without proportionally increasing chip area, as corners utilize otherwise underutilized space.
Solution Approach 2:
The patent employs asymmetric pad placement strategies where command/address pads are positioned on specific sides while data signal pads are arranged on other sides and corners. This asymmetric arrangement optimizes wiring length uniformity for data signals while maintaining compact chip dimensions by strategically placing different pad types in different locations rather than uniform distribution.
2Area of moving object
If bond fingers are densely arranged to reduce chip area, then chip area is reduced, but wiring length uniformity deteriorates
Solution Approach 1:
The patent segments the bond finger arrangement into different regions: dense arrangements in areas where wiring length control is less critical, and more spaced arrangements in regions where uniform wiring length is essential for high-speed data signals. This segmented approach achieves wiring length uniformity while maintaining overall compact chip area.
Solution Approach 2:
The patent applies different bond finger spacing strategies in different local regions of the chip. Areas requiring precise wiring length control (data signal regions) have bond fingers positioned to facilitate uniform wiring, while other regions use denser arrangements to minimize area. This local optimization resolves the contradiction between area and wiring uniformity.
3Reliability
If additional bond fingers are added for power supply reinforcement, then power supply capability is improved, but available space for data signal bond fingers is reduced
Solution Approach 1:
The patent merges power supply bond fingers with data signal bond finger arrangements by positioning power supply pads adjacent to data signal pads on the chip perimeter. This integrated arrangement allows both power supply reinforcement and data signal connectivity without requiring separate dedicated spaces, effectively combining both functions within the same peripheral region.
Solution Approach 2:
The patent creates multi-functional pad regions where certain peripheral locations serve dual purposes: providing both power supply connections and data signal connections. This universal approach allows the same chip perimeter region to fulfill multiple functions, eliminating the need to choose between power supply capability and data signal capability.
Data Source
AI summary
Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.